Built-in self-test emulator
OwnerElias Gedamu, Denise Maninventors
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Abstract
Systems, methods, and a computer program are disclosed. One embodiment comprises a compiler for developing verification tests of an integrated circuit. The compiler comprises an interface and a built-in self-test (BIST) emulator. The interface includes an input and an output. The interface receives and forwards operator-level instructions to the BIST emulator, which is coupled to the output. The BIST emulator simulates the operation of a BIST module within the integrated circuit. The BIST emulator includes a function that initializes a plurality of indicators associated with respective data storage locations in communication with the integrated circuit in response to the operator level instruction.
Claims19
A compiler for developing a test for verifying operational performance of an integrated circuit, the compiler comprising:
- an interface having an input and an output, the interface configured to receive and forward instructions;
- and
- a built-in self-test (BIST) emulator coupled to the output of the interface, the BIST emulator configured to generate at least one hardware-level instruction responsive to an operator level instruction received at the interface, the BIST emulator comprising a function that initializes a plurality of indicators associated with respective data storage locations in communication with the integrated circuit in response to the operator level instruction.
A method for developing verification and performance tests of a processor, the method comprising:
- providing a compiler configured to simulate the operation of a built-in self-test (BIST) module within the processor, the compiler comprising a function that initializes a plurality of indicators each associated with a respective data storage location in communication with the processor;
- applying an operator level instruction to the compiler;
- observing at least one status indicator responsive to execution of at least one hardware-level instruction, wherein the hardware-level instruction is responsive to the operator level instruction;
- and
- determining whether the at least one status identifier is indicative of an expected condition.
A program embodied in a computer-readable medium, the program comprising:
- logic configured to generate at least one hardware-level instruction responsive to an operator level instruction;
- logic configured to apply the at least one hardware-level instruction to a built-in self test (BIST) emulator, the BIST emulator comprising a function that initializes a plurality of indicators associated with respective data storage locations;
- logic configured to monitor the status of at least one data storage location;
- and
- logic configured to determine whether the status of the at least one data storage location is indicative of an expected condition.
A compiler, comprising:
- means for emulating a built-in self test (BIST) module associated with an integrated circuit, wherein the means for emulating a BIST module includes a function that initializes a plurality of indicators associated with respective data storage locations in communication with the integrated circuit;
- and
- means for applying a hardware-level instruction to the means for emulating a BIST module responsive to an operator level instruction.
Dependencies are inferred from the claim text.