Logic analyzer data processing method
AssigneeZeroplus Technology Co., Ltd.
InventorsChiu-Hao Cheng, Ming-Gwo Cheng, Tsung-Chih Huang, Chun-Feng Tzu
Life of this patent
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Abstract
A logic analyzer data processing method used in a logic analyzer (10) having a control circuit (17) adapted to read in test data from a test sample (13), a memory (18) controlled by the control circuit (17) to store the test data received from the test sample (13), and a display (161) adapted to display the test data fetched by the control circuit (17) from the memory (18), the method including the step of enabling the control circuit (17) to drive a compressor (19) to compress the test data received from the test sample (13) before storing it in the memory (18), and to depress the compressed test data before transmitting it from the memory (18) to the display (161).
Claims22
A logic data analyzer for a test sample, comprising:
- a control circuit adapted for reading a test data from said test sample;
- a memory, having a predetermined memory space, controlled by said control circuit to store said test data;
- a compressor electrically coupled between said control circuit and said memory to compress said test data for reducing a size thereof before storing in said memory, such that said compressed test data is stored in said memory space of said memory to maximize said memory space of said memory to be utilized for storing a complete series of said test data of said test sample;
- and
- a transmission interface electrically connected to said control circuit for communicating connecting to a computer having a display means, wherein when said memory space of said memory is used up, said control circuit fetches said test data in said memory for directly transmitting said fetched test data to said computer through said transmission interface so as to display said fetched test data on said display means.
The logic data analyzer, as recited in claim 2, wherein said control circuit controls said compressor for decompressing said fetched test data before transmitting said fetched test data to said computer.
A logic data analyzer for a test sample, comprising:
- a control circuit adapted for reading a test data from said test sample;
- a memory, having a predetermined memory space, controlled by said control circuit to store said test data;
- a compressor electrically coupled between said control circuit and said memory to compress said test data for reducing a size thereof before storing in said memory, such that said compressed test data is stored in said memory space of said memory to maximize said memory space of said memory to be utilized for storing a complete series of said test data of said test sample;
- and
- a display means electrically coupling with said compressor, wherein when said memory space of said memory is used up, said control circuit fetches said test data in said memory to display said fetched test data on said display panel.
A method of processing a test data from a test sample to a logic data analyzer which comprises a control circuit, a memory, and a compressor, comprising the steps of:
- (a) reading said test data from said test sample to said control circuit;
- (b) compressing said test data by said compressor to reduce a size of said test data;
- (c) storing said compressed test data in said memory to maximize a memory space of said memory to be utilized for storing a complete series of said test data of said test sample;
- and
- (d) displaying said test data on a display means which is electrically coupled with said compressor, wherein when said memory space of said memory is used up, said control circuit fetches said test data in said memory to display said fetched test data on said display panel.
Dependencies are inferred from the claim text.