Cache coherency during resynchronization of self-correcting computer

A method of restoring synchronous operation of a plurality of processors in a computer system, the method comprising:

• determining an instance of internal processor state data in accordance with processor majority vote of the plurality of processors;
• storing the instance;
• disabling caches of the processors of the plurality of processors;
• after the steps of disabling caches, disabling cache snooping;
• after the step of disabling cache snooping, resetting each processor of the plurality of processors;
• after the step of resetting, loading said each processor of the plurality of processors with the instance of the flushed out internal processor state data;
• after the step of loading, enabling cache snooping;
• after the step of enabling cache snooping, enabling the caches of the processors of the plurality of processors;
• causing the processors of the plurality of processors to operate synchronously in parallel to execute application code.

A fault-tolerant computer system comprising:

• a plurality of processors configured to operate synchronously in parallel;
• multi-module redundancy logic configured to receive outputs of the processors, and determine majority processor vote for each of the outputs;
• and
• resynchronization state machine configured to
• determine an instance of internal processor state data in accordance with processor majority vote of the plurality of processors,
• store the instance,
• disable caches of the processors of the plurality of processors,
• disable cache snooping after disabling caches,
• reset each processor of the plurality of processors after disabling cache snooping,
• after resetting, load said each processor with the stored instance,
• enable snooping after loading said each processor of the plurality of processors with the stored instance, and
• enable the caches of the processors of the plurality of processors after enabling snooping,
• whereby the resynchronization state machine restores synchronous operation of the plurality of processors and prevents snooping while the processors come out of reset.

A fault-tolerant computer system comprising:

• a plurality of processors configured to operate synchronously in parallel;
• means for receiving outputs of the processors, and for determining majority processor vote for each of the outputs;
• and
• resynchronization means for synchronizing operation of the plurality of processors and preventing snooping by external devices during time periods when the processors are in reset and initialize coming out of reset.