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US 2006/0143428 A1Published application
Semiconductor signal processing device
AssigneeRenesas Technology Corp.
InventorsHideyuki Noda, Kazutami Arimoto, Katsumi Dosaka, Kazunori Saito
Life of this patent
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Abstract
An orthogonal memory for transforming arrangements of system bus data and processing data is placed between a system bus interface and a memory cell mat storing the processing data. The orthogonal memory includes two-port memory cells, and changes data train transferred in a bit parallel and word serial fashion into a data train of word parallel and bit serial data. Data transfer efficiency in a signal processing device performing parallel operational processing can be increased without impairing parallelism of the processing.
Claims13
A semiconductor signal processing device comprising:
- at least one fundamental operational block including a memory cell mat divided into a plurality of entries each having a plurality of memory cells, and a plurality of processing units, arranged corresponding to the entries of said memory cell mat, each being capable of performing an operational processing on data of a corresponding entry and storing a result of said the operational processing in the corresponding entry, each of said entries storing bits of a same multi-bit data;
- an internal data transfer bus for transferring data of a larger bit width than external transfer data outside the device with the memory cell mat of the fundamental operational block;
- an interface unit for providing an external interface with an outside of the device;
- data arrangement transforming circuitry arranged between said interface unit and said internal data transfer bus for rearranging the data between said interface unit and said internal data transfer data bus,
- said data arrangement transforming circuitry including
- a plurality of first word lines arranged extending in a first direction in which the entries extends,
- a plurality of second word lines arranged extending in a second direction crossing the first direction,
- a plurality of first bit line pairs arranged extending in said second direction,
- a plurality of second bit line pairs arranged extending in said first direction, and
- a memory array having a plurality of Static Random Access Memory (SRAM) cells arranged being aligned in the first and second directions into an array form and located corresponding to crossings of the first word lines and the first bit line pairs and crossings of the second word lines and the second bit line pairs, the first word lines being arranged corresponding to the second bit line pairs, and the second word lines being arranged corresponding to the first bit line pairs,
- first cell selecting circuitry for selecting a first word line in the first word line and a fist bit line pair among the first bit line when data is transferred with said interface unit, and
- second cell selecting circuitry for selecting a second word line in the second word lines and a second bit line in the second bit line pair when the data is transferred with said internal data transfer bus.
9 more elements
A semiconductor signal processing device comprising:
- a fundamental operational block including a memory array divided into a plurality of entries each having a plurality of memory cells aligned in a first direction, and a plurality of operational processing units, arranged corresponding to the entries of said memory array, each being capable of performing an operational processing on data of a corresponding entry and of storing a result of the operational processing in the corresponding entry, each of said entries storing bits of same multi-bit data;
- data arrangement transforming circuitry arranged adjacently and corresponding to said memory array for rearranging the data between an internal data bus and said memory array,
- said data arrangement transforming circuitry including:
- a plurality of first word lines arranged corresponding to the entries,
- a plurality of second word lines arranged extending in a second direction crossing the first direction,
- a plurality of first bit line pairs arranged extending in said second direction,
- a plurality of second bit line pairs arranged extending in said first direction and corresponding to the entries, and
- a memory cell array having a plurality of Static Random Access Memory (SRAM) cells arranged being aligned in the first and second directions into an array form and located corresponding to crossings of the first word lines and the first bit line pairs and crossings of the second word lines and the second bit line pairs, the first word lines being arranged corresponding to the second bit line pairs, and the second word lines being arranged corresponding to the first bit line pairs,
- first cell selecting circuit for selecting a first word line in the first word lines and a fist bit line pair in the first bit line pairs when data is transferred with said internal data bus,
- second cell selecting circuit for selecting a second word line in the second word lines and a second bit line pair in the second bit line pairs when the data is transferred with r from the memory array of the fundamental operational block, and
- data transferring circuit for transferring data between the entries and corresponding second bit lines.
8 more elements
Dependencies are inferred from the claim text.