Efficient usage of last level caches in a MCMP system using application level configuration
AssigneeIntel Corporation
InventorKrishnakanth Sistla
Life of this patent
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Abstract
This disclosure presents an architectural mechanism which allows a caching bridge to efficiently store data either inclusively or exclusively based upon information configured by an application. An INC bit is set for each access to a page table that indicates whether the data is shared or not shared by a LLC. This allows a multicore multiprocessor system to have a caching policy which enables use of the last level cache efficiently and results in improved performance of the multicore multiprocessor system.
Claims34
A method comprising:
- determining space required by an application for a transaction;
- configuring the application for the transaction, wherein configuring comprises setting a bit based on space required by the application to indicate whether the application prefers an inclusive or exclusive space for the transaction.
A processor comprising:
- a page table in the processor stores a bit for a transaction to indicate if attributes of the transaction are inclusive or exclusive.
The processor of 13 wherein the bridge further comprises a first queue for requests originating from the core.
A multicore multiprocessor system comprising:
- a first core comprising:
- a page table, in the first core, stores a bit for a transaction to indicate if attributes of the transaction are inclusive or exclusive.
- a first interface to a second core;
- a second interface coupled to input/output devices;
- and
- an audio input/output device coupled to the second interface.
Dependencies are inferred from the claim text.