Data processing device

Abstract

A data processor has a central processing unit and a plurality of logical blocks (1104) to be connected to the central processing unit, and the central processing unit sets a predetermined logical block to be a control object based on a result of decode of a predetermined instruction code (CBP) and a function of the predetermined logical block is selected based on the result of decode of the predetermined instruction code and a part of address information which is incidental to the predetermined instruction code (TAG [14:13]). It is possible to decide an operating object in an early stage before reaching a memory access stage of a pipeline without requiring to allocate the instruction code in a one-to-one correspondence for the operation of the predetermined logical block. Consequently, it is possible to suppress a consumption of the instruction code, a useless power consumption and a reduction in a processing performance of an operation for a specific logical block, for example, a cache coherency operation or a TLB page attribute operation in the same operation.

Dependencies are inferred from the claim text.