System and method for cache coherency in a cache with different cache location lengths
AssigneeIntel Corporation
InventorsYen-Kuang Chen, Christopher Hughes, James Tuck
Life of this patent
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Abstract
A system and method for the design and operation of a cache system with differing cache location lengths in level one caches is disclosed. In one embodiment, each level one cache may include groups of cache locations of differing length, capable of holding portions of a level two cache line. A state tree may be created from data in a sharing vector. When a request arrives from a level one cache, the level two cache may examine the nodes of the state tree to determine whether the node of the state tree corresponding to the incoming request is already active. The results of this determination may be used to inhibit or permit the concurrent processing of the request.
Claims31
A processor, comprising:
- a first core with a first cache including a first group of cache locations of a first length and a second group of cache locations of a second length;
- a second cache at a hierarchy level further from said first core than said first cache, with a third group of cache locations of a third length;
- and
- a first logic to perform coherency operations, to hold a directory entry of a first cache line in one of said third group of cache locations with fields corresponding to cache lines in said first cache.
A method, comprising:
- receiving a request for a memory or cache operation from one of a group of first level caches each including cache locations of a first length and cache locations of a second length;
- determining in a second level cache which of said cache locations of said first length and said cache locations of said second length include portions of a first cache line of said second level cache corresponding to said request;
- and
- delaying said request for said memory or cache operation based in part on results of said determining.
A system, comprising:
- a processor including a first core with a first cache including a first group of cache locations of a first length and a second group of cache locations of a second length, a second cache at a hierarchy level further from said first core than said first cache, with a third group of cache locations of a third length, and a first logic to perform coherency operations, to hold a directory entry of a first cache line in one of said third group of cache locations with corresponding fields to cache lines in said first cache;
- an interconnect to couple said processor to an input/output device;
- and
- a network controller coupled to said processor by said interconnect.
An apparatus, comprising:
- means for receiving a request for a memory or cache operation from one of a group of first level caches each including cache locations of a first length and cache locations of a second length;
- means for determining in a second level cache which of said cache locations of said first length and said cache locations of said second length include portions of a first cache line of said second level cache corresponding to said request;
- and
- means for delaying said request for said memory or cache operation based in part on results produced by said means for determining.
Dependencies are inferred from the claim text.