Method and apparatus for prefetching based on cache fill buffer hits
OwnerJacob Doweck, Ehud Cohen +1inventors
InventorsJacob Doweck, Ehud Cohen, Ziv Barukh
Life of this patent
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Abstract
An apparatus and method for prefetching based on fill buffer hits is disclosed. In one embodiment, a processor includes a cache fill buffer and a prefetcher. The cache fill buffer has a number of fill buffer entry locations. Each load entry location is to store a load entry, including an address of data to be loaded into a cache. The prefetcher generates, in response to an instruction needing data from a first address, a request to prefetch data from a second address, if one of the cache fill buffer entries corresponds to the first address.
Claims23
A processor comprising:
- a cache fill buffer having a plurality of fill buffer entry locations;
- and
- a prefetcher to generate, in response to an instruction needing data from a first address, a request to prefetch data from a second address if the cache fill buffer includes an entry in one of the plurality of fill buffer entry locations corresponding to the first address.
A processor comprising:
- a cache fill buffer having a plurality of fill buffer entry locations;
- a register to store a configuration parameter N;
- and
- a prefetcher to generate, in response to an Nth instruction needing data from a first address, a request to prefetch data from a second address if the cache fill buffer includes an entry in one of the plurality of fill buffer entry locations corresponding to the first address.
A system comprising:
- a dynamic random access memory;
- a level two cache coupled to the dynamic random access memory;
- a first processor coupled to the level two cache, including:
- a first cache fill buffer having a first plurality of fill buffer entry locations to fill a first level one cache;
- and
- a first prefetcher to generate, in response to the first processor needing data from a first address, a first request to prefetch data from a second address if the first cache fill buffer includes an entry in one of the first plurality of fill buffer entry locations corresponding to the first address;
- and
- a second processor coupled to the level two cache, including:
- a second cache fill buffer having a second plurality of fill buffer entry locations to fill a second level one cache;
- and
- a second prefetcher to generate, in response to the second processor needing data from a third address, a second request to prefetch data from a fourth address if the second cache fill buffer includes an entry in one of the second plurality of fill buffer entry locations corresponding to the third address.
A method comprising:
- receiving an instruction needing data from a first address;
- and
- generating a request to prefetch data from a second address if an entry corresponding to the first address is stored in a cache fill buffer.
Dependencies are inferred from the claim text.