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US 2006/0143400 A1Published application
Replacement in non-uniform access cache structure
OwnerSimon Steelyinventor
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Abstract
An embodiment of the present invention is a technique to perform replacement in a non-uniform access cache structure. A cache memory stores data and associated tags in a non-uniform access manner. The cache memory has a plurality of memory banks arranged according to a distance hierarchy with respect to one of a processor and a processor core. The distance hierarchy includes a lowest latency bank and a highest latency bank. A controller performs a non-uniform pseudo least recently used (LRU) replacement on the cache memory.
Claims30
An apparatus comprising:
- a cache memory to store data and associated tags in a non-uniform access manner, the cache memory having a plurality of memory banks arranged according to a distance hierarchy with respect to a processor, the distance hierarchy including a lowest latency bank and a highest latency bank;
- and
- a controller coupled to the cache memory to perform a non-uniform pseudo least recently used (LRU) replacement on the cache memory.
A method comprising:
- storing data and associated tags in a cache memory in a non-uniform access manner, the cache memory having a plurality of memory banks arranged according to a distance hierarchy with respect to a processor, the distance hierarchy including a lowest latency bank and a highest latency bank;
- and
- performing a non-uniform pseudo least recently used (LRU) replacement on the cache memory.
A system comprising:
- a processor having a processor core;
- a main memory coupled to the processor;
- and
- a cache structure coupled to one of the processor and the processor core and the main memory, the cache structure comprising:
- a cache memory to store data and associated tags in a non-uniform access manner, the cache memory having a plurality of memory banks arranged according to a distance hierarchy with respect to the one of the processor and the processor core, the distance hierarchy including a lowest latency bank and a highest latency bank, and
- a controller coupled to the cache memory to perform a non-uniform pseudo least recently used (LRU) replacement on the cache memory.
3 more elements
Dependencies are inferred from the claim text.