Dirty line hint array for cache flushing
OwnerR. O'Bleness, Sujat Jamil +2inventors
InventorsR. O'Bleness, Sujat Jamil, Quinn Merrell, Hang Nguyen
Life of this patent
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Abstract
Techniques for using a dirty line hint array when flushing a cache are disclosed. In one embodiment, an apparatus includes a number of hint bits. Each hint bit corresponds to a number of cache lines, and indicates whether at least one of those cache lines is dirty.
Claims13
An apparatus comprising a plurality of hint bits, where each hint bit corresponds to a plurality of lines in a cache and indicates whether at least one of the plurality of lines is dirty.
A method comprising:
- identifying a cache line during a cache flush;
- reading a hint bit, where the hint bit corresponds to a plurality of cache lines, including the identified cache line, and indicates whether at least one of the plurality of cache line is dirty;
- determining not to write back the identified cache line if the hint bit is clean, without accessing the cache to read the dirty bit corresponding to the identified cache line.
A method comprising:
- comparing a high order portion of look-up data to a shared high order portion of stored data, where the shared high order portion is shared by a plurality of entry locations in a content addressable memory;
- comparing a low order portion of look-up data to a low order portion of each of the plurality of entry locations;
- and
- generating a plurality of hit signals, one for each of the plurality of entry locations, each based on the comparison to the shared high order portion of stored data.
A method comprising:
- comparing a high order portion of look-up data to a high order portion of a first entry in a content addressable memory;
- disabling the logic to compare the high order portion of look-up date to the high order portion of a second entry in the content addressable memory if a prevalidation bit is set;
- comparing a low order portion of look-up data to a low order portion of the second entry location;
- and
- generating a hit signal for the second entry location based on the comparison to the high order portion of the first entry and the low order portion of the second entry.
A system comprising:
- a first processor;
- a cache coupled to the first processor;
- and
- a hint array including a plurality of hint bits, where each hint bit corresponds to a plurality of lines in the cache and indicates whether at least one of the plurality of lines is dirty.
A system comprising:
- a dynamic random access memory;
- a cache coupled to the dynamic random access memory;
- a processor coupled to the cache;
- and
- a hint array including a plurality of hint bits, where each hint bit corresponds to a plurality of lines in the cache and indicates whether at least one of the plurality of lines is dirty.
A machine-readable medium carrying instructions which, when executed by a processor, cause the processor to:
- identify a cache line during a cache flush;
- read a hint bit, where the hint bit corresponds to a plurality of cache lines, including the identified cache line, and indicates whether at least one of the plurality of cache line is dirty;
- determine not to write back the identified cache line if the hint bit is clean, without accessing the cache to read the dirty bit corresponding to the identified cache line.
Dependencies are inferred from the claim text.