System and method for non-uniform cache in a multi-core processor

A method, comprising:

• searching for a first cache line in cache tiles associated with a first processor core;
• if said first cache line is not found in said cache tiles associated with said first processor core, then sending a request for said first cache line to sets of cache tiles associated with processor cores other than said first processor core;
• and
• tracking responses from said sets of cache tiles using a register.

A system, comprising:

• a processor including a set of processor cores coupled via an interface, and a set of cache tiles that may be searched in parallel, where a first cache tile and a second cache tile of said set is to receive a first cache line, and where a distance from a first core of said set of processor cores to said first cache tile and said second cache tile is different;
• a system interface to couple said processor to input/output devices;
• and
• a network controller to receive signals from said processor.

An apparatus, comprising:

• means for searching for a first cache line in cache tiles associated with a first processor core;
• means for, if said first cache line is not found in said cache tiles associated with said first processor core, then sending a request for said first cache line to a set of processor cores;
• and
• means for tracking responses from said set of processor cores using a register.