Content addressable memory with shared comparison logic

A method comprising:

• comparing a high order portion of look-up data to a shared high order portion of stored data, where the shared high order portion is shared by a plurality of entry locations in a content addressable memory;
• comparing a low order portion of look-up data to a low order portion of each of the plurality of entry locations;
• and
• generating a plurality of hit signals, one for each of the plurality of entry locations, each based on the comparison to the shared high order portion of stored data.

A method comprising:

• comparing a high order portion of look-up data to a high order portion of a first entry in a content addressable memory;
• disabling the logic to compare the high order portion of look-up date to the high order portion of a second entry in the content addressable memory if a prevalidation bit is set;
• comparing a low order portion of look-up data to a low order portion of the second entry location;
• and
• generating a hit signal for the second entry location based on the comparison to the high order portion of the first entry and the low order portion of the second entry.

A system comprising:

• a dynamic random access memory;
• and
• a processor including a content addressable memory having:
• a first entry location including:
• a first plurality of cells to store a high order portion of a first entry;
• and
• first comparison logic to indicate whether a first condition is true, where the first condition is whether a first portion of look-up data matches the high order portion of the first entry;
• a second entry location including:
• a second plurality of cells to store the low order portion of a second entry;
• second comparison logic to indicate whether a second condition is true, where the second condition is whether a second portion of look-up data matches the low order portion of the second entry;
• and
• first match logic to indicate whether both the first condition and the second condition are true.