Memory device, memory managing method and program
AssigneeTokyo Electron Device Limited
InventorSyuichi Kikuchi
Life of this patent
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AssigneeTokyo Electron Device Limited
InventorSyuichi Kikuchi
Estimating the term…
Disclosed is a memory device which is not easily deteriorated and a memory managing method which does not easily deteriorate a memory device. A physical address is given to a memory area of a flash memory (11) page by page. When supplied with to-bewritten data and a logical address where the data is to be written, a CPU (121) writes this data in a page indicated by a write pointer. The correlation between the physical address and the logical address of the page is stored in a RAM (123) in the form of BPT (Block Pointer Table). At the time of reading, the CPU (121) that has been supplied with the logical address searches the BPT to specify a physical address associated with that logical address and reads data from that page which is given the specified physical address. Flash erasing of a block is executed when the number of empty blocks becomes equal to or smaller than a predetermined number.
A memory device characterized by comprising:
A memory managing method for managing a non-volatile memory having a plurality of memory blocks for storing data to which physical addresses are allocated, and each of said memory blocks including physical pages, each of said physical pages including a logical page and a redundancy portion, characterized in that
A program for allowing a computer (121), connected to a memory (11) including a plurality of memory blocks for storing data to which physical addresses are allocated, to function to:
Dependencies are inferred from the claim text.