Synchronizing multiple threads efficiently
AssigneeIntel Corporation
InventorsSailesh Kottapalli, John Crawford
Life of this patent
Estimating the term…
Abstract
In one embodiment, the present invention includes a method of assigning a location within a shared variable for each of multiple threads and writing a value to a corresponding location to indicate that the corresponding thread has reached a barrier. In such manner, when all the threads have reached the barrier, synchronization is established. In some embodiments, the shared variable may be stored in a cache accessible by the multiple threads. Other embodiments are described and claimed.
Claims29
A method comprising:
- assigning a location within a shared variable for each of multiple threads;
- and
- writing a value to a corresponding location to indicate that a corresponding thread reached a barrier.
A method comprising:
- associating a single variable with a data structure having a plurality of data elements;
- and
- locking at least one of the plurality of data elements using the single variable.
An article comprising a machine-readable storage medium containing instructions that if executed by a machine enable the machine to perform a method comprising:
- executing a plurality of threads of a program;
- and
- storing a first value in a first portion of a shared variable when a first thread reaches a barrier of the program.
An apparatus comprising:
- a cache coupled to a first processor and a second processor to store a shared memory structure having a plurality of portions, wherein each of the plurality of portions corresponds to one of a plurality of threads of a program.
A system comprising:
- a first processor;
- a second processor coupled to the first processor;
- a cache coupled to the first processor and the second processor to store a first shared variable having a plurality of portions, each of the plurality of portions corresponding to one of a plurality of data elements of a first data structure;
- and
- a dynamic random access memory coupled to the cache.
An apparatus comprising:
- a first processor core;
- a second processor core coupled to the first processor core;
- and
- a cache coupled to the first processor core and the second processor core to store a first shared memory structure having a plurality of portions, wherein each of the plurality of portions corresponds to one of a plurality of threads of a program executed on the first processor core and the second processor core.
Dependencies are inferred from the claim text.