Display controller
AssigneeSeiko Epson Corporation
InventorsYoshimasa Kondo, Yasuhiko Hanawa
Life of this patent
Estimating the term…
Abstract
A display controller including: a host I/F which performs interface processing between the display controller and a host CPU; a memory into which a multimedia processing program is loaded, when the host CPU has read the multimedia processing program from a multimedia processing program group stored in a host memory and transmitted the multimedia processing program to the display controller; a built-in CPU which executes a software processing portion of the multimedia processing assigned to software processing based on the multimedia processing program; and an H/W accelerator which executes a hardware processing portion of the multimedia processing assigned to hardware processing.
Claims18
A display controller for performing multimedia processing which is encoding or decoding processing of video data, still image data, or sound data, the display controller comprising:
- a host interface which performs interface processing between the display controller and a host processor;
- a memory into which a multimedia processing program is loaded, when the host processor has read the multimedia processing program from a multimedia processing program group stored in a host memory and transmitted the multimedia processing program to the display controller;
- a built-in processor which executes a software processing portion of the multimedia processing assigned to software processing based on the loaded multimedia processing program;
- and
- a first hardware accelerator which executes a hardware processing portion of the multimedia processing assigned to hardware processing.
A display controller for performing multimedia processing which is encoding or decoding processing of video data, still image data, or sound data, the display controller comprising:
- a host interface which performs interface processing between the display controller and a host processor;
- a memory into which a multimedia processing program is loaded, the multimedia processing program being read by the host processor selectively from a multimedia processing program group stored in a host memory and transmitted to the display controller from the host processor;
- a built-in processor which executes a software processing portion of the multimedia processing assigned to software processing based on the loaded multimedia processing program;
- and
- a first hardware accelerator which executes a hardware processing portion of the multimedia processing assigned to hardware processing.
Dependencies are inferred from the claim text.