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US 2006/0143334 A1Published application
Efficient buffer management
OwnerUday Naikinventor
Life of this patent
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Abstract
In general, in one aspect, the disclosure describes an apparatus that includes a receiver to receive data. A plurality of queues are used to store the data. The apparatus also includes at least one processor to process the data and a transmitter to transmit the data. The apparatus further includes a buffer manager to maintain availability of the buffers and to allocate free buffers. The buffer manager includes a bit vector stored in local memory for maintaining availability status of the plurality of buffers.
Claims30
An apparatus comprising
- a receiver to receive data;
- at least one processor to process the data;
- a transmitter to transmit the data;
- a plurality of buffers to store the data while the data is being handled by the apparatus;
- and
- a buffer manager to manage availability of the buffers and to allocate free buffers, wherein said buffer manager includes a bit vector stored in local memory for maintaining availability status of said plurality of buffers.
3 more elements
A method comprising:
- receiving data for processing;
- allocating a next available buffer for storage of the data, wherein the next available buffer is allocated based on availability of a plurality of buffers that is tracked in a locally stored bit vector;
- and
- storing the data in the allocated next available buffer.
1 more element
A method comprising,
- tracking occupancy status of a plurality of buffers in a bit vector stored in local memory of a buffer manager;
- and
- performing an operation on the bit vector to determine a next available buffer.
An apparatus comprising
- a receiver to receive data and store data in buffers for processing;
- at least one processor mircoengine to process the data;
- a transmitter to remove the data from the buffers and transmit the data;
- and
- a buffer manager microengine to maintain availability status of the buffers and to allocate next free buffers to said receiver, wherein said buffer manager includes a hierarchical bit vector stored in local memory for maintaining availability status of the buffers.
2 more elements
A store and forward device comprising
- a plurality of interface cards, wherein the interface cards include network processors, and wherein the network processors include
- a receiver to receive data;
- at least one processor to process the data;
- a transmitter to transmit the data;
- and
- a buffer manager to maintain availability of a plurality of buffers and to allocate free buffers, wherein said buffer manager includes a bit vector stored in local memory for maintaining availability status of the plurality of buffers;
- and
- a crosspoint switch fabric to provide selective connectivity between said interface cards.
5 more elements
Dependencies are inferred from the claim text.