I/O hub resident cache line monitor and device register update
AssigneeIntel Corporation
InventorsDave Minturn, James Crossland, Sujoy Sen, Greg Cummings
Life of this patent
Estimating the term…
Abstract
The apparatus and method described herein are for enabling cacheable writes to I/O device registers. A cache monitor, which may be present in a controller hub, monitors accesses to cache lines in a microprocessor. The cache monitor also associates cache lines in the microprocessor with I/O device registers. When an access to certain cache lines are detected, the cache monitor is operable to receive the contents of the cache line and write those contents to an associated I/O device register. Therefore, a microprocessor may write to a cache line, instead of making an uncacheable write to the I/O device register directly.
Claims35
An apparatus comprising:
- a table to associate a data location in a first device with a second device;
- and
- logic to monitor accesses to the data location, the logic to receive data written to the data location and to write the data to the second device, when the data location is accessed.
An apparatus comprising:
- a table in a controller hub to be coupled between a microprocessor and an input/output (I/O) device, the table comprising a plurality of entries, each entry to store at least (1) an address of a cache line in the microprocessor, (2) a corresponding address of a device register in the I/O device, and (3) a value to write to the device register;
- and
- logic in the controller hub associated with the table to (1) monitor accesses to the cache line in the microprocessor, (2) store the value in the table entry, and (3) write the value to the device register.
An system comprising:
- a microprocessor having a cache, the cache having a plurality of cache lines;
- and
- a controller hub coupled to the microprocessor through an interconnect, the controller hub comprising a cache monitor, wherein the cache monitor maps a first line of the plurality of cache lines to a device register in an I/O device coupled to the controller hub.
A method comprising:
- determining if a first cache line that a value is being written to is within a first range of cache lines;
- and
- triggering a monitor entry associated with the first cache line into a data expected state, storing the value in the monitor entry, and writing the value to a device register in an input/output (I/O) device, if the first cache line is within the first range of cache lines.
A method comprising:
- executing an input/output (I/O) device driver using a microprocessor;
- detecting an access to a first line of a cache within the microprocessor during the execution of the device driver using monitor logic;
- triggering a cache monitor entry, associated with the first line of the cache, to enter a data expected state upon detection of the access to the first data location;
- writing a first value, stored in the cache monitor entry, to a device register in an I/O device.
Dependencies are inferred from the claim text.