Direct memory access circuit and disk array device using same
AssigneeFujitsu Limited
InventorsHidenori Takahashi, Yuichi Ogawa, Terumasa Haneda
Life of this patent
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Abstract
A DMA circuit prevents an erroneous data transfer by a descriptor due to an address failure of memory. When a descriptor is created, the data processing unit writes a pointer, for storing the descriptor, in a predetermined part of the descriptor, and stores the descriptor in memory, and when a DMA engine reads the descriptor from the memory, the DMA engine confirms whether the value is correct, and judges whether a DMA transfer of the data in the memory is possible. For both reading and writing of a descriptor, data corruption due to an address failure can be prevented.
Claims20
A DMA circuit for reading descriptors for indicating the DMA transfer content written by a data processing unit, reading data in an address defined by a descriptor from memory, and transferring the data, comprising:
- first and second registers for storing a top pointer and a bottom pointer of a plurality of descriptors in said memory written by said data processing unit;
- a transfer circuit for reading the descriptor of said memory indicated by said bottom pointer, analyzing the descriptor thus read, reading data in an address specified by said descriptor of said memory, and transferring the data;
- and
- a comparison circuit for comparing a descriptor pointer included in the read descriptor and said bottom pointer, and controlling the transfer operation of said transfer circuit.
A disk array apparatus comprising:
- a plurality of disk devices;
- and
- a control unit for reading/writing data of said disk device according to a request from a host,
- wherein said control unit comprises:
- a data processing unit;
- a cache memory for storing data for said disk device;
- and
- a DMA circuit for reading a descriptor to indicate the DMA transfer content written by said data processing unit, reading the data in an address defined by a descriptor from said cache memory, and transferring the data,
- and wherein said DMA circuit comprising:
- first and second registers for storing a top pointer and a bottom pointer of a plurality of descriptors that are written in said cache memory by said data processing unit;
- a transfer circuit for reading a descriptor of said cache memory indicated by said bottom pointer, analyzing the descriptor, reading the data in an address specified by said descriptor of said cache memory, and transferring the data;
- and
- a comparison circuit for comparing a descriptor pointer included in said read descriptor and said bottom pointer, and controlling the transfer operation of said transfer circuit.
Dependencies are inferred from the claim text.