Method and apparatus for performing a multiplication or division operation in an electronic circuit
AssigneeInfineon Technologies AG
InventorsChristian Drewes, Ernst Bodenstorfer, Jurgen Niederholz
Life of this patent
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Abstract
A multiplication or division operation X·K or X·1/K is performed in an electronic circuit. A software circuit area of the circuit calculates a digit shift sv such that psv is an approximate value for K. In a hardware circuit area, the value X is shifted sv digits to the left in the case of multiplication or sv digits to the right in the case of division. The software circuit area calculates a suitable correction factor Kf. The value X is multiplied by the correction factor Kf.
Claims20
A method for performing a multiplication or division operation comprising:
- calculating a digit shift sv in a software circuit area of an electronic circuit wherein psv is an approximate value for a normalization factor K, where p is a base;
- shifting an accumulated data stream X to the left by the digit shift sv for multiplication or to the right by the digit shift sv for division within a hardware circuit area of the electronic circuit to obtain a shifted value;
- calculating a correction factor Kf in the software circuit area;
- or
- multiplying the shifted value by the correction factor Kf to obtain a final value.
A method for performing a multiplication or division operation comprising:
- calculating a digit shift according to an approximate value for a normalization factor;
- shifting an accumulated data stream according to the calculated digit shift to obtain a shifted value;
- calculating a correction factor;
- and
- multiplying the shifted value by the correction factor to obtain a final value.
An electronic circuit for performing a multiplication or a division operation comprising:
- a software circuit area;
- a hardware circuit area coupled to the software circuit area;
- a first calculation mechanism located in the software circuit area for calculating a digit shift sv wherein psv is an approximate value for a normalization factor K, where p is a base;
- a controllable digit shifter located within the hardware circuit area for shifting an accumulated data stream X to the left by the digit shift sv for multiplication or to the right by the digit shift sv for division to obtain a shifted value;
- a second calculation mechanism located within the software circuit area for calculating a correction factor Kf;
- and
- a multiplication mechanism for multiplying the shifted value by the correction factor Kf to obtain a final value.
Dependencies are inferred from the claim text.