Frequency synthesizer for dual mode receiver

In a portable dual mode receiver circuit, a clock system comprising:

• a baseband clock circuit;
• a multiplier circuit coupled to the clock circuit for multiplying a baseband clock by a multiplier value to a master clock frequency which has as factors a first integer divider of a first channel spacing of a first band, and a second integer divider of a second channel spacing of a second band;
• a programmable reference divider coupled to receive a clock signal of said master clock frequency, said programmable divider being selectively operative at said first integer divider value and at said second integer divider value to produce respectively said first channel spacing clock signal and said second channel spacing clock signal;
• a digital phase detector coupled to receive output of said programmable reference divider to detect phase of said first channel spacing clock signal and said second channel spacing clock signal, said digital phase detector also having as a reference input a digital feedback signal, said digital phase detector producing as output an analog phase error signal in form of a steering voltage;
• a voltage controlled oscillator (VCO) coupled to receive said phase error signal for generating a frequency controlled analog radio frequency (RF) signal at a desired frequency for system output;
• and
• a programmable VCO divider circuit coupled to receive said analog RF signal, said programmable VCO divider circuit operative to divide frequency of said analog RF signal by a first channel integer and a second channel integer, said first and second channel integers in combination with said respective first integer divider value and said second integer divider value designate a specific channel selection in the form of said digital feedback signal.

In a portable dual mode receiver circuit, a method for selecting channels using a clock system comprising the steps of:

• generating a baseband clock signal;
• multiplying said baseband clock signal by a multiplier value to a master clock frequency which has as factors a first integer divider of a first channel spacing of a first band, and a second integer divider of a second channel spacing of a second band;
• programmably dividing a clock signal of said master clock frequency selectively at said first integer divider value and at said second integer divider value to produce respectively said first channel spacing clock signal and said second channel spacing clock signal;
• detecting digitally phase of said first channel spacing clock signal and said second channel spacing clock signal, with respect a reference input of a digital feedback signal, to produce as output an analog phase error signal in form of a steering voltage;
• generating a frequency controlled analog radio frequency (RF) signal at a desired frequency for system output from a voltage controlled oscillator (VCO) coupled to receive said phase error signal;
• and
• dividing frequency of said analog RF signal respectively by a first channel integer and a second channel integer in a programmable VCO divider circuit coupled to receive said analog RF signal, said first and second channel integers corresponding in combination to said respective first integer divider value and said second integer divider value to designate a specific channel selection in the form of said digital feedback signal.