Copper electrodeposition in microelectronics
AssigneeEnthone Inc.
InventorsVincent Paneccasio, Xuan Lin, Paul Figura, Richard Hurtubise
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Abstract
An electrolytic plating method and composition for electrolytically plating Cu onto a semiconductor integrated circuit substrate having submicron-sized interconnect features. The composition comprises a source of Cu ions and a suppressor compound comprising polyether groups. The method involves superfilling by rapid bottom-up deposition at a superfill speed by which Cu deposition in a vertical direction from the bottoms of the features to the top openings of the features is substantially greater than Cu deposition on the side walls.
Claims35
An electrolytic plating composition for electrolytically plating Cu onto a semiconductor integrated circuit substrate having a planar plating surface and submicron-sized interconnect features by immersion of the semiconductor integrated circuit substrate into the electrolytic solution, the composition comprising:
- a source of Cu ions in an amount sufficient to electrolytically deposit Cu onto the substrate and into the electrical interconnect features;
- and
- a suppressor compound comprising a compound selected from the group consisting of:
- (i) a first suppressor compound comprising a combination of propylene oxide (P0) repeat units and ethylene oxide (EO) repeat units present in a PO:EO ratio between about 1:9 and about 9:1 and bonded to a nitrogen-containing species, wherein the molecular weight of the first suppressor compound is between about 1000 and about 3600 g/mol;
- (ii) a second suppressor compound comprising a combination of propylene oxide (PO) repeat units and ethylene oxide (EO) repeat units present in a PO:EO ratio between about 1:9 and about 9:1 and bonded to a nitrogen-containing species, wherein the molecular weight of the second suppressor compound is between about 1000 and about 30,000 g/mol, and wherein the second suppressor compound further comprises a capping moiety selected from the group consisting of an alkyl group or a block polymer comprising propylene oxide repeat units;
- (iii) a third suppressor compound comprising a combination of propylene oxide (PO) repeat units and ethylene oxide (EO) repeat units present in a PO:EO ratio between about 1:9 and about 9:1 and bonded to a nitrogen-containing species which is an alkylether amine, wherein the molecular weight of the third suppressor compound is between about 1000 and about 30,000 g/mol;
- and
- (iv) combinations thereof.
A method for electroplating a copper deposit onto a semiconductor integrated circuit device substrate with electrical interconnect features including submicron-sized features having bottoms, sidewalls, and top openings, the method comprising:
- immersing the semiconductor integrated circuit device substrate including submicron-sized features having bottoms, sidewalls, and top openings wherein said submicron-sized features include high aspect ratio features having dimensions such that the high aspect ratio features have aspect ratios of at least about 3:1 into an electrolytic plating composition comprising a source of Cu ions in an amount sufficient to electrolytically deposit Cu onto the substrate and into the electrical interconnect features and a suppressor compound comprising a combination of propylene oxide (PO) repeat units and ethylene oxide (EO) repeat units present in a PO:EO ratio between about 1:9 and about 9:1 and bonded to a nitrogen-containing species, wherein the molecular weight of the suppressor compound is between about 1000 and about 30,000;
- and
- supplying electrical current to the electrolytic composition to deposit Cu onto the substrate and superfill the submicron-sized features by rapid bottom-up deposition at a rate of growth in the vertical direction which is greater than a rate of growth in the horizontal direction.
A method for electroplating a copper deposit onto a semiconductor integrated circuit device substrate with electrical interconnect features including submicron-sized features having bottoms, sidewalls, and top openings, the method comprising:
- immersing the semiconductor integrated circuit device substrate into the electrolytic plating composition comprising a source of Cu ions in an amount sufficient to electrolytically deposit Cu onto the substrate and into the electrical interconnect features, an accelerator, and a suppressor;
- and
- supplying electrical current to the electrolytic composition to deposit Cu onto the substrate and superfill the submicron-sized features by rapid bottom-up deposition at a vertical Cu deposition growth rate in features from the bottoms of the features to the top openings of the features which is greater than 50% faster than a comparable vertical Cu deposition growth rate of comparable process which is equivalent in all respects except that it employs a comparative suppressor having the formula:
- wherein the sum of e+f+g=21 and the sum of h+i+j=27.
A method for electroplating a copper deposit onto a semiconductor integrated circuit device substrate with electrical interconnect features including submicron-sized features having bottoms, sidewalls, and top openings, the method comprising:
- immersing the semiconductor integrated circuit device substrate into the electrolytic plating composition comprising a source of Cu ions in an amount sufficient to electrolytically deposit Cu onto the substrate and into the electrical interconnect features, an accelerator, and a suppressor;
- and
- supplying electrical current to the electrolytic composition to deposit Cu onto the substrate and superfill the submicron-sized features by rapid bottom-up deposition at a vertical Cu deposition growth rate in features from the bottoms of the features to the top openings of the features which is greater than 15 times faster than a field deposition growth rate on substrate surfaces outside the features.
An electrolytic plating composition for electrolytically plating Cu onto a semiconductor integrated circuit substrate having a planar plating surface and submicron-sized interconnect features by immersion of the semiconductor integrated circuit substrate into the electrolytic solution, the composition comprising:
- a source of Cu ions in an amount sufficient to electrolytically deposit Cu onto the substrate and into the electrical interconnect features;
- a leveler comprising a reaction product of benzyl chloride and hydroxyethyl polyethylenimine;
- and
- a suppressor compound comprising a combination of propylene oxide (PO) repeat units and ethylene oxide (EO) repeat units present in a PO:EO ratio between about 1:9 and about 9:1 and bonded to a nitrogen-containing species, wherein the molecular weight of the suppressor compound is between about 1000 and about 30,000.
Dependencies are inferred from the claim text.