Interlocking via for package via integrity

An interconnection structure of a microelectronic package comprising:

• a first conductive layer defining a recess therein;
• a dielectric layer disposed on the first conductive layer and defining a hole therein, the hole and the recess being in communication with one another such that the recess defines an interlocking volume under the dielectric layer;
• a second conductive layer disposed on the dielectric layer;
• and
• a package via comprising a conductive material that substantially fills the hole of the dielectric layer and the recess of the first conductive layer, the package via extending from the second conductive layer through the hole of the dielectric layer to the recess of the first conductive layer to define an interlocking section under the dielectric layer.

A system comprising:

• an electronic assembly including a microelectronic package, the package having an interconnection structure therein comprising:
• a first conductive layer defining a recess therein;
• a dielectric layer disposed on the first conductive layer and defining a hole therein, the hole and the recess being in communication with one another such that the recess defines an interlocking volume under the dielectric layer;
• a second conductive layer disposed on the dielectric layer;
• and
• a package via comprising a conductive material that substantially fills the hole of the dielectric layer and the recess of the first conductive layer, the package via extending from the second conductive layer through the hole of the dielectric layer to the recess of the first conductive layer to define an interlocking section under the dielectric layer;
• and
• a graphics processor coupled to the electronic assembly.