Formation of junctions and silicides with reduced thermal budget
AssigneeKoninklijke Philips Electronics N.V.
InventorBartlomiej Pawlak
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Abstract
Method of formation of a metal-silicide layer (12, 13, 14, 18, 19) an a semiconductor substrate (1), the semiconductor substrate (1) including at least a dopant region (5); the dopant region (5) including an ultra-shallow junction region; the method including as a first step at least one impurity implantation process (IB dopant) for forming the dopant region (5); the method including as a second step at least one metal implantation process (IB metal) for forming the metal-silicide layer (12, 13, 18, 19) an the dopant region (5), and the method including, as a third step carried out after the first and the second step, a low-temperature annealing process wherein simultaneously the dopant region (5) is activated and the metal-silicide layer (12, 13, 14, 18, 19) is formed.
Claims14
Method of manufacturing a semiconductor device comprising the step of forming a metal-silicide layer on a semiconductor substrate,
- said semiconductor substrate comprising at least a dopant region;
- said dopant region comprising an ultra-shallow junction region;
- said method comprising as a first step at least one impurity implantation process for forming said dopant region;
- said method comprising as a second step at least one metal implantation process for forming said metal-silicide layer on said dopant region
- characterized in that said method is arranged to carry out after said first and said second step:
- as a third step a low-temperature annealing process wherein simultaneously said dopant region is activated and said metal-silicide layer is formed.
Dependencies are inferred from the claim text.