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US 2006/0141727 A1Published application
Method of fabricating low-power CMOS device
AssigneeDongbu Electronics Co., Ltd.
InventorEun Shin
Life of this patent
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Abstract
A low-power CMOS device can be fabricated by forming a shallow trench on a silicon substrate using a gate mask and negative photoresist. This enables an extremely low profile for a junction after completion of lightly doped drain and source/drain implantations. The method includes forming a shallow trench in a silicon substrate.
Claims10
A method of fabricating a low-power CMOS device, comprising:
- providing a silicon substrate;
- and
- forming a shallow trench in the silicon substrate using a gate mask and negative photoresist.
Dependencies are inferred from the claim text.