Method for manufacturing a cell transistor of a semiconductor memory device

Abstract

Disclosed is a method for manufacturing a cell transistor of a semiconductor memory device. The method comprises the steps of: forming device isolation films and a well on a semiconductor substrate; forming a threshold voltage adjust region by ion-implanting a first conductive impurity dopant into the well of the semiconductor substrate; performing a first thermal annealing on the semiconductor substrate where the threshold voltage adjust region is formed; forming a gate insulating film and gate electrodes on top of the semiconductor substrate between the device isolation films; forming a halo ion implantation region by ion-implanting a first conductive impurity dopant into the semiconductor substrate corresponding to a drain region exposed by the gate electrodes; performing a second thermal annealing on the semiconductor substrate where the halo ion implantation region is formed; and forming source/drain regions by ion-implanting a second conductive impurity dopant into the semiconductor substrate exposed by the gate electrodes. This method can reduce the turn-off leakage current of the cell transistor since the dopant dose of the threshold voltage adjust region can be reduced while maintaining the threshold voltage by increasing the dopant diffusion of the threshold voltage adjust region.

Dependencies are inferred from the claim text.