US 2006/0141714 A1 · Method for manufacturing a semiconductor device

Abstract

An exemplary method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a P-well and an N-well for high voltage (HV) devices and a first well in a low voltage/medium voltage (LV/MV) region for a logic device, in a semiconductor substrate; simultaneously forming a second well in the LV/MV region for a logic device and a drift region for one of the HV devices using the same mask; and respectively forming gate oxide layers on the semiconductor substrate in the HV/MV/LV regions. According to the present invention, the number of photolithography processes can be reduced by replacing or combining an additional mask for forming an extended drain region of a high voltage depletion-enhancement CMOS (DECMOS) with a mask for forming a typical well of a logic device, so productivity of the total process of the device can be enhanced.

Claims12

Dependent claims

A method of manufacturing a semiconductor device, comprising:

forming a P-well and an N-well for a plurality of high voltage (HV) devices;
forming a first well in a low voltage and/or medium voltage (LV/MV) region of a semiconductor substrate for one or more logic devices;
simultaneously forming a second well in the LV/MV region for one of the one or more logic devices and a drift region for one of the HV devices using the same mask;
and
forming one or more gate oxide layers on the semiconductor substrate for the HV devices and in the, MV and LV regions.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

11/319,814Filed 27 Dec 2005

Priority

KR 10-2004-011564129 Dec 2004

Published

29 Jun 2006

Term ends

Not estimatedThe source records don’t support an estimate.

Classification5 codes

H10D 84/017
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their source or drain regions, e.g. silicided source or drain regions
H10D 84/0181
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their gate insulating layers
H10D 84/0191
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their doped wells
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe

Method for manufacturing a semiconductor device

Life of this patent

Method for manufacturing a semiconductor device

Life of this patent

Abstract

Claims12