Non-volatile memory device with buried control gate and method of fabricating the same

A non-volatile memory device having a buried control gate comprising:

• a semiconductor substrate;
• a control gate disposed within a trench formed in the semiconductor substrate;
• a drain region formed in the semiconductor device spaced apart from the control gate by a distance;
• a source region formed in the semiconductor device adjacent another side of the control gate;
• a tunnel oxide layer, a charge trapping layer and a blocking oxide layer on the semiconductor substrate and the control gate;
• and
• a word gate on the blocking oxide layer over the control gate.

A method of fabricating a non-volatile memory device with a buried control gate comprising:

• sequentially stacking a first oxide layer, a first nitride layer and a disposable oxide layer on a semiconductor substrate;
• patterning the semiconductor substrate with the disposable oxide layer thereon to form a trench by partially etching the semiconductor substrate, and forming a channel oxide layer within the trench;
• depositing a polysilicon layer for a control gate on the channel oxide layer by filling the trench and planarizing the polysilicon layer;
• forming a spacer using the disposable oxide layer at a side of the polysilicon layer;
• forming source/drain regions in the semiconductor substrate via ion implanting, using the spacer as a mask;
• removing the spacer, an upper portion of the polysilicon layer, the first nitride layer and the first oxide layer disposed on the semiconductor substrate;
• sequentially forming a tunnel oxide layer, a charge trapping layer, and a blocking oxide layer on the semiconductor substrate and a remaining lower portion of the polysilicon layer comprising the control gate;
• and
• forming a word gate on the blocking oxide layer.

A method of fabricating a non-volatile memory device with a buried control gate comprising:

• sequentially stacking a first oxide layer, a first nitride layer and a disposable oxide layer on a semiconductor substrate;
• patterning the semiconductor substrate with the disposable oxide layer thereon to form a trench by partially etching the semiconductor substrate, and forming a channel oxide layer within the trench;
• depositing a polysilicon layer for a control gate on the channel oxide layer by filling the trench and planarizing the polysilicon layer;
• forming a spacer using the disposable oxide layer at a the side of the polysilicon layer;
• forming source/drain regions in the semiconductor substrate via ion implanting, using the spacer as a mask;
• removing the spacer, an upper portion of the polysilicon layer and the first nitride layer disposed on the semiconductor substrate;
• depositing a photoresist layer on the drain region, and ion implanting the source region to be adjacent to the polysilicon layer for the control gate;
• removing the first oxide layer;
• sequentially forming a tunnel oxide layer, a charge trapping layer, and a blocking oxide layer on the semiconductor substrate and a remaining lower portion of the polysilicon layer comprising the control gate;
• and
• forming a word gate on the blocking oxide layer.