Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction

A method of forming a transistor, comprising:

• forming a trench in a silicon wafer such that a trench wall of the trench has a (110) crystal plane orientation;
• forming a first source/drain region and a second source/drain region lateral to a wall of the trench with a channel region therebetween, wherein forming each source/drain region includes:
• forming a doped material structure against the wall of the trench;
• diffusing dopants from the doped material structure into the wall of the trench;
• removing the doped material structure from the trench;
• and
• wherein the transistor is oriented to selectively conduct an electrical current across the channel region in a direction parallel to a top surface of the wafer.

A method of forming a transistor, comprising:

• forming a trench in a silicon wafer such that a trench wall of the trench has a (110) crystal plane orientation;
• forming a first source/drain region and a second source/drain region lateral to a wall of the trench with a channel region therebetween, wherein forming each source/drain region includes:
• ion implanting dopants into the wafer surface prior to forming the trench to form doped regions of a first type within a surface wafer material of a second type;
• forming the trench between ion implanted regions after formation of the doped regions;
• and
• wherein the transistor is oriented to selectively conduct an electrical current across the channel region in a direction parallel to a top surface of the wafer.

A method of forming a transistor, comprising:

• forming a trench in a silicon wafer such that a trench wall of the trench has a (110) crystal plane orientation;
• forming a first source/drain region and a second source/drain region lateral to a wall of the trench with a channel region therebetween, wherein forming each source/drain region includes angled ion implanting dopants into the trench wall to form doped regions of a first type within a wall material of a second type;
• and
• wherein the transistor is oriented to selectively conduct an electrical current across the channel region in a direction parallel to a top surface of the wafer.

A method of forming a memory device, comprising:

• forming a number of memory cells, each cell including at least one transistor, wherein forming the transistor includes:
• forming a trench in a silicon wafer such that a trench wall of the trench has a (110) crystal plane orientation;
• forming a first source/drain region and a second source/drain region lateral to a wall of the trench with a channel region therebetween;
• wherein the transistor is oriented to selectively conduct an electrical current across the channel region in a direction parallel to a top surface of the wafer;
• and
• forming storage and access circuitry coupled to the number of memory cells.

A method of forming an electronic system, comprising:

• forming a memory device coupled to a processor, wherein forming the memory device includes forming a number of memory cells, each cell including at least one transistor, wherein forming the transistor includes:
• forming a trench in a silicon wafer such that a trench wall of the trench has a (110) crystal plane orientation;
• forming a first source/drain region and a second source/drain region lateral to a wall of the trench with a channel region therebetween;
• wherein the transistor is oriented to selectively conduct an electrical current across the channel region in a direction parallel to a top surface of the wafer;
• and
• forming storage and access circuitry coupled to the number of memory cells.