Methods and systems for controlling variation in dimensions of patterned features across a wafer

Abstract

Methods and systems for controlling variation in dimensions of patterned features across a wafer are provided. One method includes measuring a characteristic of a latent image formed in a resist at more than one location across a wafer during a lithography process. The method also includes altering a parameter of the lithography process in response to the characteristic to reduce variation in dimensions of patterned features formed across the wafer by the lithography process. Altering the parameter compensates for non-time varying spatial variation in a temperature to which the wafer is exposed during a post exposure bake step of the lithography process and an additional variation in the post exposure bake step.

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