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US 2006/0140324 A1Published application
Clock recovery apparatus, method, and system
AssigneeIntel Corporation
InventorsBryan Casper, Aaron Martin, Stephen Mooney, James Jaussi
Life of this patent
Estimating the term…
Abstract
A global clock recovery circuit and port circuit determine and combine static phase adjustment information and dynamic phase adjustment information for multiple data signals. Static phase adjustment information is determined for each of the multiple data signals, and dynamic phase adjustment information is determined in common for the multiple data signals.
Claims27
An apparatus comprising:
- a first loop circuit to receive a reference clock and produce at least one internal clock signal;
- a plurality of second loop circuits, wherein each of the plurality of second loop circuits is coupled to receive the at least one internal clock signal and a data signal, and to provide a phase offset indication;
- and
- a finite state machine to receive the phase offset indication from each of the plurality of second loop circuits, and to provide phase adjustment information to each of the plurality of second loop circuits.
1 more element
An integrated circuit comprising:
- a port circuit including a plurality of loop circuits to receive a plurality of data signals;
- and
- a global clock recovery circuit coupled to receive a reference signal and to recover a clock frequency from the reference signal, and further coupled to receive phase offset information from each of the plurality of loop circuits.
A method comprising:
- receiving a reference clock signal;
- receiving a training sequence on a plurality of data input nodes;
- recovering a clock frequency from the reference clock signal;
- and
- determining a separate static phase adjustment for each of the plurality of data input nodes, the static phase adjustment for a clock signal to clock a data signal on each of the plurality of data input nodes.
2 more elements
An electronic system comprising:
- a first integrated circuit having a first port circuit to transmit a plurality of data signals;
- a second integrated circuit having a second port circuit with a plurality of loop circuits coupled to the first port circuit of the first integrated circuit, and having a global clock recovery circuit coupled to receive a reference signal and to recover a clock frequency from the reference signal, and further coupled to receive phase offset information from each of the plurality of loop circuits;
- and
- an antenna coupled to the first integrated circuit.
1 more element
Dependencies are inferred from the claim text.