Reducing phase offsets in a phase detector
AssigneeSilicon Laboratories Inc.
InventorAdam Eldredge
Life of this patent
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Abstract
In one embodiment, the present invention includes a system having an amplifier to receive an incoming signal and a recovery circuit coupled to the amplifier that includes a phase detector to adjust a phase of a sampling clock via a signal indicative of a difference between transitions occurring between the sampling clock and each of a first error clock and a second error clock. Based on a phase adjusted output of the phase detector, the sampling clock may be generated with an appropriate phase. Thus, circuitry and methods are provided to reduce or eliminate phase offsets in the phase detector.
Claims28
A method comprising:
- combining transitions between a sampling clock and each of a first error clock and a second error clock to obtain an error count and comparing a target error count with the error count to obtain an error signal;
- filtering the error signal to obtain an offset signal;
- and
- adjusting a phase of at least one of the first error clock and the second error clock using the offset signal.
A method comprising:
- determining a difference in transitions between a sampling clock and each of a first error clock and a second error clock;
- filtering the difference;
- and
- adjusting a phase of the sampling clock using the filtered difference.
An integrated circuit comprising:
- a phase detector to adjust a phase of a sampling clock via receipt of a first signal indicative of a difference in transitions between the sampling clock and each of a first error clock and a second error clock;
- a first filter coupled to filter an output of the phase detector;
- and
- a first phase interpolator coupled to the first filter to generate the sampling clock.
An integrated circuit comprising:
- a first combiner to obtain a difference between a first error clock transition count and a second error clock transition count;
- and
- a first filter coupled to receive and filter the difference to generate a first signal.
A system comprising:
- an amplifier to receive an incoming signal;
- and
- a recovery circuit coupled to the amplifier, the recovery circuit comprising:
- a phase detector to adjust a phase of a sampling clock via receipt of a phase adjust signal indicative of a difference in transitions between the sampling clock and each of a first error clock and a second error clock;
- a first filter coupled to filter an output of the phase detector;
- and
- a first phase interpolator coupled to the first filter to generate the sampling clock.
Dependencies are inferred from the claim text.