Processor-controlled clock-data recovery
AssigneeRambus Inc.
InventorsStephen Tell, Thomas Greer
Life of this patent
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Abstract
A processor-controlled clock-data recovery (CDR) system. Phase error signals having either a first state or a second state are generated within the CDR system according to whether a first clock signal leads or lags transitions of a data signal. A difference value is generated based on the phase error signals, the difference value indicating a difference between the number of the phase error signals having the first state and a number of the phase error signals having the second state. The difference value is transferred to a processor which is programmed to determine whether the difference value exceeds a first threshold and, if so, to adjust the phase of the first clock signal.
Claims36
A method of operation within a clock-data recovery (CDR) system, the method comprising:
- generating phase error signals having a first state or a second state according to whether a first clock signal leads or lags transitions of a data signal;
- generating a difference value that indicates a difference between a number of the phase error signals having the first state and a number of the phase error signals having the second state;
- transferring the difference value to a processor;
- determining, within the processor, whether the difference value exceeds a first threshold;
- and
- adjusting the phase of the first clock signal if the difference value exceeds the first threshold.
An integrated circuit device comprising:
- a phase detecting circuit to generate phase error signals having a first state or a second state according to whether a first clock signal leads or lags transitions of a data signal;
- a difference generating circuit to generate a difference value that indicates a difference between a number of the phase error signals having the first state and a number of phase error signals having the second state;
- and
- a processor coupled to receive the difference value from the difference generating circuit, the processor being programmed to determine whether the difference value exceeds a first threshold and to adjust the phase of the first clock signal if the difference value exceeds the first threshold.
An integrated circuit device comprising:
- means for generating phase error signals having a first state or a second state according to whether a first clock signal leads or lags transitions of a data signal;
- means for generating a difference value that indicates a difference between a number of the phase error signals having the first state and a number of the phase error signals having the second state;
- means for transferring the difference value to a processor;
- means, within the processor, for determining whether the difference value exceeds a first threshold;
- and
- means for adjusting the phase of the first clock signal if the difference value exceeds the first threshold.
Computer-readable media having information embodied therein that includes a description of at least a portion of an integrated circuit device, the information including descriptions of:
- a phase detecting circuit to generate phase error signals having a first state or a second state according to whether a first clock signal leads or lags transitions of a data signal;
- a difference generating circuit to generate a difference value that indicates a difference between a number of the phase error signals having the first state and a number of phase error signals having the second state;
- and
- a processor coupled to receive the difference value from the difference generating circuit, the processor being programmed to determine whether the difference value exceeds a first threshold and to adjust the phase of the first clock signal if the difference value exceeds the first threshold.
Dependencies are inferred from the claim text.