Calibrating a phase detector and analog-to-digital converter offset and gain
AssigneeSilicon Laboratories Inc.
InventorsAdam Eldredge, Jeffrey Batchelor, Gary Hammes
Life of this patent
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Abstract
The present invention includes apparatus and methods to calibrate a phase detector and an analog-to-digital converter (ADC) offset and gain. In one such embodiment, an apparatus includes a phase detector to generate an error pulse and a reference pulse, a combiner to combine the pulses, and an ADC to receive the combined pulses, where the ADC has a full scale set by an average of the reference pulse. Still further, a calibration loop may be coupled between the output of the ADC and the phase detector to generate and provide a phase adjust signal to reduce or eliminate phase offsets. Other embodiments are described and claimed.
Claims30
An apparatus comprising:
- a phase detector to generate an error pulse and a reference pulse;
- a combiner to combine the error pulse and the reference pulse into a phase detector pulse;
- and
- an analog-to-digital converter (ADC) coupled to receive the phase detector pulse, the ADC having a full scale set by an average of the reference pulse.
An apparatus comprising:
- a phase detector to generate a phase detector pulse;
- an analog-to-digital converter (ADC) coupled to receive the phase detector pulse;
- and
- a calibration loop coupled to receive an output of the ADC and to generate a phase adjust value to force an average value of the ADC output to be substantially zero.
A method comprising:
- sweeping a phase of a sampling clock across a data eye during calibration of a phase detector;
- and
- filtering a value corresponding to an output of the phase detector.
A system comprising:
- an amplifier to receive optical energy and convert the optical energy to electrical energy;
- a phase detector coupled to the amplifier to generate a phase detector pulse;
- an analog-to-digital converter (ADC) coupled to receive the phase detector pulse;
- and
- a calibration loop coupled to receive an output of the ADC and to generate a phase adjust value to force a filtered value of the ADC output to be substantially zero.
Dependencies are inferred from the claim text.