Amplitude monitor for high-speed signals

A method of detecting an input signal on an input port, the method comprising:

• a. generating a sample clock signal defining a plurality of sample instants;
• b. sampling a voltage on the input port at the plurality of sample instants over a sample period, the sampling including comparing the voltage on the input port with a reference at each of the sample instants;
• and
• c. indicating a presence of the input signal when the voltage on the input port exceeds the threshold at a first of the sample instants during the sample period and falls below the threshold at a second of the sample instants during the sample period.

A communication system comprising:

• a. a transmitter at times providing a transmitted signal, timed to a reference clock, on a transmitter output port, the transmitted signal including a plurality of data symbols;
• b. a communication channel coupled to the transmitter output port to convey the transmitted signal;
• and
• c. a receiver coupled to the communication channel to receive the transmitted signal, the receiver including:
• i. an input port coupled to the communication channel to receive the transmitted signal, the input port to exhibit an input-port voltage above a threshold voltage in response to the transmitted signal and below the threshold voltage absent the transmitted signal;
• ii. a sampler, coupled to the input port, to sample the input-port voltage, the sampler to provide sampled data;
• iii. a clock-recovery circuit coupled to the sampler, the clock-recovery circuit to develop a recovered-clock signal from the sampled data and to apply the recovered-clock signal to the sampler;
• iv. a sample-clock source generating a sample clock signal including a plurality of sample-clock edges, each of the sample-clock edges having a different phase relationship with respect to the recovered clock signal irrespective of the presence of the transmitted signal;
• and
• v. an amplitude detector having an amplitude-detector input port coupled to the communication channel and to receive the transmitted signal, a reference port to receive a reference, and a clock node coupled to the sample-clock source to receive the sample clock signal, the amplitude detector to sample a level on the channel irrespective of the presence of the transmitted signal upon edges of the sample clock signal over a sample period;
• vi. wherein the amplitude detector detects the transmitted signal if the amplitude detector samples at least one of the data symbols over the sample period.

A receiver detecting an absence of an input signal, the receiver comprising:

• a. an input port to receive the input signal;
• b. a sampler coupled to the input port to receive the input signal, the sampler including a recovered-clock terminal and an output port;
• c. clock recovery circuitry coupled between the output port of the sampler and the recovered-clock terminal of the sampler, the clock recovery circuitry developing a recovered-clock signal in the absence of the input signal, the clock recovery circuitry to synchronize the recovered-clock signal with the input signal;
• d. means for generating a sample clock signal in the absence of the input signal, the sample clock signal including a plurality of sample-clock edges, each of the sample-clock edges having a different phase relationship with respect to the recovered-clock signal;
• and
• e. an amplitude detector having an amplitude-detector input port coupled to the input port, the amplitude detector detecting the input signal and noting the absence of the input signal.

A computer-readable medium having stored thereon a data structure defining an amplitude monitor, the data structure comprising:

• a. first data representing an input port to receive an input signal, the input port to exhibit an input-port voltage above a threshold voltage in response to the input signal and below the threshold voltage in an absence of the input signal;
• b. second data representing a sampler having a sampler port coupled to the input port, a recovered-clock terminal, and a sampler output port, the sampler to sample the input-port voltage to recover the input signal when present on the input port;
• c. third data representing a clock-recovery circuit coupled to the sampler output terminal, the clock-recovery circuit to develop a recovered-clock signal from the recovered input signal and to apply the recovered-clock signal to the recovered-clock terminal of the sampler;
• d. fourth data representing a sample-clock generator to generate a sample clock signal having a plurality of sample-clock edges phase shifted with respect to the input signal by a plurality of phase shifts;
• and
• e. fifth data representing an amplitude detector, coupled to the input port, to sample the input port voltage over a sample period and in response to the sample-clock edges, the amplitude detector to detect the absence of the input signal.