Clock synchronization circuit

Abstract

A clock synchronization circuit for synchronizing a first clock signal (Φ1) and a second clock signal (Φ2) for data transfer from a first function block (2), which is clocked by the first clock signal (ΦD) at a relatively high clock frequency (fΦ1), to a second function block (3), which is clocked by the second clock signal (Φ2) at a relatively low clock frequency (fΦ2), where the clock synchronization circuit (24) has a sampling unit (30) for sampling the second clock signal (Φ2) using the first clock signal (Φ1) in order to generate samples (S) and edge detection values (E) of the sampled second clock signal (Φ2), a logic circuit (38), clocked using the first clock signal (Φ1), for outputting the generated samples (S) or the generated edge detection values (E) as a reconstructed second clock signal (Φ2′) in the time frame of the first clock signal (Φ1) at an output of the logic circuit (38), where the output (42) of the logic circuit is reset after outputting a value (S, E) until the logic circuit (38) receives an Enable signal, where the logic circuit (38) generates an Edge-Too-Early signal (ETE) if the generated edge detection value (E) is at logic high before the Enable signal is received, and generates an Edge-Too-Late signal (ETL) if the Enable signal is received before the generated edge detection value (E) is at logic high, and a signal delay circuit, clocked using the first clock signal (Φ1), which delays the reconstructed second clock signal (Φ2′) with a variable time delay (τ) on the basis of the Edge-Too-Early signal (ETE) and the Edge-Too-Late signal (ETL).

Dependencies are inferred from the claim text.