Clock and data recovery circuits
AssigneeIndustrial Technology Research Institute
InventorsChun-Cheng Kuo, Li-Ren Huang
Life of this patent
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Abstract
A clock and data recovery circuit comprising a phase detection circuit, first and second oscillators, and a flip-flop. The phase detection circuit outputs a detection signal according to a significant transition of an input signal. Each oscillator receives the detection signal and operates alternately in a clock and data recovery mode and a phase-locked mode. When the first oscillator operates in the clock and data recovery mode and outputs a first clock to control the flip-flop to output an output signal, the second oscillator operates in the phase-locked mode to adjust a frequency of a second clock. Before switching to the clock and data recovery mode, the second oscillator synchronizes the second clock with the first clock.
Claims28
A clock and data recovery circuit receiving an input signal and outputting an output signal in phase with the input signal, comprising:
- a phase detection circuit estimating a significant transition of the input signal and outputting a first detection signal;
- a first oscillator receiving the first detection signal and outputting a first clock, wherein the first oscillator operates in a first mode during a first period and sequentially in second and synchronization modes during a second period;
- a second oscillator receiving the first detection signal and outputting a second clock, wherein the second oscillator operates sequentially in the second and synchronization modes during the first period and operates in the first mode during the second period;
- and
- a flip-flop receiving the input signal and outputting the output signal according to the first and second clocks respectively during the first and second periods.
A clock and data recovery circuit receiving an input signal and outputting an output signal in phase with the input signal, comprising:
- a phase detection circuit estimating a significant transition of the input signal and outputting a detection signal;
- first and second oscillators, each receiving the detection signal and operating alternately in a clock and data recovery mode and a phase-locked mode, wherein the first and second oscillators respectively output first and second clocks;
- and
- a flip-flop receiving the input terminal and outputting the output signal according to the first or second clock;
- wherein during a first period, the first oscillator operates in the clock and data recovery mode and outputs the first clock to control the flip-flop to output the output signal, and the second oscillator operates in the phase-locked mode to adjust a frequency of the second clock;
- and
- wherein during the first period, before switching to the clock and data recovery mode, the second oscillator synchronizes the second clock with the first clock.
Dependencies are inferred from the claim text.