Synchronous storage device and control method therefor
AssigneeSpansion LLC
InventorShimbayashi Koji
Life of this patent
Estimating the term…
Abstract
In a DDR operation mode, (L−1) count signal BRDYB is inverted to a low level when 1 is subtracted from initial latency (e.g., L=3). As a result, a delayed signal S (N1BD)/S (N1D) in reverse phase to signal S (N1)/S (N1B) is provided and internal clock signal CKI becomes high during the high level period of the second cycle. This is operated in synchronization with both edges of the external clock signal CLK, and output of double the frequency is started. In the external clock signal cycle immediately before completion of counting of initial latency in a count period for initial latency, the internal clock signal CKI is changed over to double the frequency. Validity flag RDY is changed to a high level during a second cycle of the double frequency.
Claims32
A synchronous storage device capable of switching between a first operation mode for accessing in synchronism with either edge of a pulse of an external clock signal and a second operation mode for accessing in synchronism with both edges of a pulse of the external clock signal, the synchronous storage device comprising:
- an L−n detector for counting pulses of the external clock signal while counting the initial latency (L) from start of accessing, and detecting the number of pulses of the external clock signal (L−n) by subtracting n, wherein n is a numerical value of 1 or greater in increments of 0.5, from the initial latency (L);
- and
- an internal clock signal generator coupled to the L−n detector for switching an internal clock signal from a first clock signal for synchronizing with either edge of a pulse of the external clock signal to a second clock signal for synchronizing with both edges of a pulse of the external clock signal, in response to the detected signal from the L−n detector when the second operation mode is being set.
A synchronous storage device for accessing in synchronism with both edges of an external clock signal comprising:
- a basic clock signal generator for providing a pulse signal in response to a signal synchronizing with one edge of the external clock signal and a delayed signal in reverse phase to the signal;
- a half-period notice unit for providing a half-period signal by detecting the timing of a half period from one edge of the external clock signal;
- and
- a first intermediate clock signal generator for providing a pulse signal in response to the half-period signal and a delayed signal in reverse phase to the half-period signal,
- wherein a second clock signal is generated in response to the pulse signals provided from the basic clock signal generator and the first intermediate clock signal generator.
A control method of a synchronous storage device capable of switching between a first operation mode for accessing in synchronism with either edge of an external clock signal and a second operation mode for accessing in synchronism with both edges of the external clock signal, the control method comprising the steps of:
- detecting the number of clock signals (L−n), by subtracting n (n having a numerical value of 1 or higher at increments of 0.5) from the initial latency (L), about the external clock signal, the initial latency (L) being counted from start;
- and
- in the second operation mode, switching the internal clock signal from a first clock signal for synchronizing with either edge of the external clock signal to a second clock signal for synchronizing with both edges of the external clock signal in response to the step of detecting the number of clock signals (L−n).
A control method of a synchronous storage device for accessing in synchronism with both edges of an external clock signal, the control method comprising the steps of:
- obtaining an internal clock signal by generating a pulse signal in response to a signal synchronizing with one edge of the external clock signal and a delayed signal in reverse phase to the signal;
- detecting the timing of a half period from one edge of the external clock signal;
- and
- generating a pulse signal and adding to the internal clock signal in response to a signal obtained at the step of detecting the timing of the half period and a delayed signal in reverse phase to the signal.
Dependencies are inferred from the claim text.