Flash memory architecture for optimizing performance of memory having multi-level memory cells

Abstract

A flash memory device having a pipelined RAS/CAS architecture is logically organized as an array of rows and columns of multi-bit flash memory cells each capable of being selectively programmed to have a threshold voltage corresponding to one of a plurality of multi-bit bit-sets. In one embodiment, the memory device is adapted to perform a burst read operation in which a row of flash memory cells is sensed and latched and subsequently outputted from the device on consecutive clock cycles following a sense latency period. In accordance with one aspect of the invention, the pipelined architecture allows for a second burst read operation to be initiated prior to completion of the first, such that the sense latency periods for all but the first of a series of successive burst read operations are hidden, enabling the memory device to perform comparably to a memory device having conventional flash memory cells.

Dependencies are inferred from the claim text.