Memory with selectable single cell or twin cell configuration
AssigneeInfineon Technologies AG
InventorsThomas Vogelsang, Harald Lorenz, Wolfgang Hokenmaier
Life of this patent
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Abstract
A memory circuit comprises a memory including a memory array, a twin cell mode predecoder, and a row address predecoder. The memory array comprises word lines. The twin cell mode predecoder is configured for selecting one of four word line activation configurations for the memory array. The four word line activation configurations include three twin cell word line activation configurations and a single cell word line activation configuration. The row address predecoder is configured for selecting one of four word lines if the single cell word line activation configuration is selected.
Claims34
A memory circuit comprising:
- a memory including a memory array, the memory array comprising word lines;
- a twin cell mode predecoder configured for selecting one of four word line activation configurations for the memory array, the four word line activation configurations including three twin cell word line activation configurations and a single cell word line activation configuration;
- and
- a row address predecoder configured for selecting one of four word lines if the single cell word line activation configuration is selected.
A dynamic random access memory comprising:
- an array of memory cells;
- and
- a word line decoder configured to selectively access the array of memory cells in one of a single cell configuration and a twin cell configuration.
A row decoder for a dynamic random access memory comprising:
- a twin cell mode predecoder configured to selectively activate one of a first mode selection signal, a second mode selection signal, a third mode selection signal, and a fourth mode selection signal;
- a first twin cell mode selection circuit configured to be activated in response to the first mode selection signal;
- a second twin cell mode selection circuit configured to be activated in response to the second mode selection signal;
- a third twin cell mode selection circuit configured to be activated in response to the third mode selection signal;
- and
- a single cell mode selection circuit configured to be activated in response to the fourth mode selection signal.
A random access memory for low power applications comprising:
- means for selecting one of a first twin cell mode, a second twin cell mode, a third twin cell mode, and a single cell mode;
- and
- means for activating selected word lines in response to the means for selecting.
A cellular random access memory comprising:
- an array of memory cells having word lines;
- and
- a row decoder coupled to the array of memory cell, the row decoder comprising:
- a twin cell mode predecoder configured to selectively activate one of a first mode selection signal, a second mode selection signal, a third mode selection signal, and a fourth mode selection signal;
- a first twin cell mode selection circuit configured to be activated in response to the first mode selection signal;
- a second twin cell mode selection circuit configured to be activated in response to the second mode selection signal;
- a third twin cell mode selection circuit configured to be activated in response to the third mode selection signal;
- and
- a single cell mode selection circuit configured to be activated in response to the fourth mode selection signal;
- a row address predecoder configured to decode a row address for the single cell mode selection circuit;
- and
- a word line decoder configured to activate selected word lines based on the activated one of the first twin cell mode selection circuit, the second twin cell mode selection circuit, the third twin cell mode selection circuit, and the single cell mode selection circuit.
A method for operating a memory, the method comprising:
- receiving a first mode selection signal;
- receiving a second mode selection signal;
- decoding the first mode selection signal and the second mode selection signal to provide one of three twin cell mode selection signals;
- passing a row address signal to provide a first pair of word line activation signals in response to the one of three mode selection signals;
- passing a complementary row address signal to provide a second pair of word line activation signals in response to the one of three mode selection signals;
- and
- activating a pair of word lines in a memory array in response to one of the first pair of word line activation signals and the second pair of word line activation signals.
A method for testing a random access memory, the method comprising:
- selecting a single cell mode for a random access memory;
- testing each memory cell in the random access memory to provide test results indicating defective memory cells;
- repairing the random access memory based on the test results by substituting redundant memory cells for defective memory cells;
- and
- selecting a twin cell mode for the random access memory.
Dependencies are inferred from the claim text.