Data bus architecture for a semiconductor memory

A method comprising the steps of:

• providing a semiconductor memory device that includes:
• a plurality of memory cells;
• a plurality of sense amplifiers coupled to the memory cells;
• a plurality of signal lines, each of the signal lines being coupled to an output of at least one of the sense amplifiers;
• and
• a plurality of isolating circuits, each of the isolating circuits being associated with one of the signal lines and isolating that signal line from the output of the sense amplifier to which it is coupled at least during an evaluating phase in which a datum stored in one of the memory cells is evaluated by that sense amplifier;
• arranging the signal lines in at least two groups such that coupling capacitances between the signal lines of the first group and the signal lines of the second group are substantially negligible;
• and
• holding the signal lines to either a first level or a second voltage level during the evaluating phase, the first voltage level corresponding to a first logic level and the second voltage level corresponding to a second logic level,
• wherein the holding step includes the sub-steps of:
• precharging the signal lines of the first group to the first voltage level;
• and
• precharging the signal lines of the second group to the second voltage level.

An information processing system including at least one semiconductor memory device, the memory device comprising:

• a plurality of memory cells;
• a plurality of sense amplifiers coupled to the memory cells;
• a plurality of signal lines, each of the signal lines being coupled to an output of at least one of the sense amplifiers;
• a plurality of isolating circuits, each of the isolating circuits being associated with one of the signal lines and isolating that signal line from the output of the sense amplifier to which it is coupled at least during an evaluating phase in which a datum stored in one of the memory cells is evaluated by that sense amplifier;
• and
• a precharging circuit for precharging the signal lines;
• wherein the plurality of signal lines comprises at least a first group of the signal lines and a second group of the signal lines, arranged such that coupling capacitances between the signal lines of the first group and the signal lines of the second group are substantially negligible, and
• the precharging circuit precharges the signal lines of the first group to a first voltage level and precharges the signal lines of the second group to a second voltage level, which is different than the first voltage level.