Method for operating a semiconductor memory apparatus, and semiconductor memory system
AssigneeInfineon Technologies AG
InventorJean-Marc Dortu
Life of this patent
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Abstract
The present invention relates to a method for operating a semiconductor memory apparatus, comprising: transmitting a command instruction, particularly a write instruction and/or a read instruction, to the semiconductor memory apparatus; transmitting a data signal to and/or from the semiconductor memory apparatus; and transmitting a data clock signal is transmitted for the purpose of latching the data signal; wherein the preamble (P), which is the number of clock cycles between the first edge of the data clock signal (WQDS) and the first bit (D0) of the data signal (DQ), can be set. The invention also relates to a semiconductor memory system comprising a semiconductor memory apparatus and a processor unit configured to perform the method.
Claims11
A method for operating a semiconductor memory apparatus, comprising:
- transmitting a command instruction to the semiconductor memory apparatus, wherein the command instruction is at least one of a write instruction and a read instruction;
- communicating a data signal with the semiconductor memory apparatus;
- transmitting a data clock signal to latch the data signal;
- and
- setting a preamble which represents a number of clock cycles between a first edge of the data clock signal and a first bit of the data signal.
A semiconductor memory system, comprising:
- a semiconductor memory apparatus;
- a processor unit which is configured to:
- transmit a command instruction to the semiconductor memory apparatus, wherein the command instruction is at least one of a write instruction and a read instruction;
- communicate a data signal with the semiconductor memory apparatus;
- transmit a data clock signal to latch the data signal;
- and
- set a preamble which represents a number of clock cycles between a first edge of the data clock signal and a first bit of the data signal.
A method for operating a semiconductor memory apparatus, comprising:
- transmitting a command instruction to the semiconductor memory apparatus, wherein the command instruction is at least one of a write instruction and a read instruction;
- communicating a data signal with the semiconductor memory apparatus;
- transmitting a data clock signal to latch the data signal;
- and
- transmitting a configuration instruction to the semiconductor memory apparatus, wherein the configuration instruction sets a mode register value selected from at least two predefined values;
- wherein each of the predefined values sets a preamble length defining a number of clock cycles between a first edge of the data clock signal and a first bit of the data signal.
Dependencies are inferred from the claim text.