US 2006/0140024 A1 · MULTI-PHASE CLOCK SIGNAL GENERATOR AND METHOD HAVING INHERENTLY UNLIMITED FREQUENCY CAPABILITY

Abstract

A delay-lock loop includes several delay lines, all but the first of which is composed of at least one variable delay unit that provides a fixed delay and a variable delay. The first delay line is composed of a plurality of fixed delay units, but no variable delay units. The remaining delay lines are each composed of different numbers of variable delay units to provide respective clock signals having different phases, but they do not include any of the fixed delay units. The first and a last delay line receive an input clock signal. Each of the remaining delay lines are coupled to an output of one of the fixed delay units depending on the number of variable delay units in the delay line so that the resulting clock signals have all been delayed the same number of fixed delay periods.

Claims52

Dependent claims

A delay-lock loop for generating a plurality of clock signals having predetermined phases relative to each other using an input clock signal, the system comprising:

a first delay line receiving the input clock signal, the first delay line generating a first clock signal by delaying the input clock signal with a delay of DF, where DF is a fixed delay time;
a second delay line receiving the input clock signal, the second delay line generating a second clock signal by delaying the input clock signal with a delay of DF+MDV, where DV is a variable delay time corresponding to a control signal applied to the second delay line and M is the ratio of the phase of the second clock signal relative to the phase of the first clock signal;
a third delay line receiving the input clock signal, the third delay line generating a third clock signal by delaying the input clock signal with a delay of DF+DV;
and
a phase detector receiving the first clock signal and the third clock signal, the phase detector being operable to generate the control signal corresponding to a difference between the phase of the first clock signal and the phase of the third clock signal.

2 more elements

A clock multiplier system for generating an output clock signal having a frequency that is a predetermined multiple of the frequency of a periodic input clock signal, the system comprising:

a first delay line receiving the input clock signal, the first delay line generating a first clock signal by delaying the input clock signal with a delay of DF, where DF is a fixed delay time;
a second delay line receiving the input clock signal, the second delay line generating a second clock signal by delaying the input clock signal with a delay of DF+MDV, where DV is a variable delay time corresponding to a control signal applied to the second delay line and M is the ratio between the phase of the second clock signal and the phase of the first clock signal;
a third delay line receiving the input clock signal, the third delay line generating a third clock signal by delaying the input clock signal with a delay of DF+DV;
a phase detector receiving the first clock signal and the third clock signal, the phase detector being operable to generate the control signal corresponding to a difference between the phase of the first clock signal and the phase of the third clock signal;
and
a logic circuit coupled to at least two of the delay lines to receive the respective clock signals from the delay lines, the logic circuit being operable to combine the clock signals from the delay lines to generate the output clock signal.

3 more elements

A memory device, comprising:

a row address circuit operable to receive and decode row address signals applied to external address terminals of the memory device;
a column address circuit operable to receive and decode column address signals applied to the external address terminals;
a memory cell array operable to store data written to and read from the array at a location determined by the decoded row address signals and the decoded column address signals
a read data path circuit operable to couple read data signals from the memory cell array to external data terminals of the memory device;
a write data path circuit operable to couple write data signals from the external data terminals of the memory device to the memory cell array;
a command decoder operable to decode a plurality of command signals applied to respective external command terminals of the memory device, the command decoder being operable to generate control signals corresponding to the decoded command signals;
and
a delay-lock loop operable to generate either a write data strobe signal or a read data strobe signal from an internal clock signal, the delay-lock loop comprising:
a first delay line receiving the internal clock signal, the first delay line generating a first clock signal by delaying the internal clock signal with a delay of DF, where DF is a fixed delay time;
a second delay line receiving the internal clock signal, the second delay line generating at least one of the write data strobe signal and the read data strobe signal by delaying the internal clock signal with a delay of DF+MDV, where DV is a variable delay time corresponding to a control signal applied to the second delay line and M is the ratio of the phase of the generated strobe signal relative to the phase of the first clock signal;
a third delay line receiving the internal clock signal, the third delay line generating a third clock signal by delaying the internal clock signal with a delay of DF+DV;
and
a phase detector receiving the first clock signal and the third clock signal, the phase detector being operable to generate the control signal corresponding to a difference between the phase of the first clock signal and the phase of the third clock signal.

10 more elements

A processor-based system, comprising

a processor having a processor bus;
an input device coupled to the processor through the processor bus adapted to allow data to be entered into the computer system;
an output device coupled to the processor through the processor bus adapted to allow data to be output from the computer system;
and
a memory device coupled to the processor bus adapted to allow data to be stored, the memory device comprising:
a row address circuit operable to receive and decode row address signals applied to external address terminals of the memory device;
a column address circuit operable to receive and decode column address signals applied to the external address terminals;
and
a memory device, comprising:
a row address circuit operable to receive and decode row address signals applied to external address terminals of the memory device;
a column address circuit operable to receive and decode column address signals applied to the external address terminals;
a memory cell array operable to store data written to and read from the array at a location determined by the decoded row address signals and the decoded column address signals;
a read data path circuit operable to couple read data signals from the array to external data terminals of the memory device;
a write data path circuit operable to couple write data signals from the external data terminals of the memory device to the array;
a command decoder operable to decode a plurality of command signals applied to respective external command terminals of the memory device, the command decoder being operable to generate control signals corresponding to the decoded command signals;
and
a delay-lock loop operable to generate either a write data strobe signal or a
read data strobe signal from an internal clock signal, the delay-lock loop comprising:
a first delay line receiving the internal clock signal, the first delay line generating a first clock signal by delaying the internal clock signal with a delay of DF, where DF is a fixed delay time;
a second delay line receiving the internal clock signal, the second delay line generating at least one of the write data strobe signal and the read data strobe signal by delaying the internal clock signal with a delay of DF+MDV, where DV is a variable delay time corresponding to a control signal applied to the second delay line and M is the ratio of the phase of the generated strobe signal relative to the phase of the first clock signal;
a third delay line receiving the internal clock signal, the third delay line generating a third clock signal by delaying the internal clock signal with a delay of DF+DV;
and
a phase detector receiving the first clock signal and the third clock signal, the phase detector being operable to generate the control signal corresponding to a difference between the phase of the first clock signal and the phase of the third clock signal.

20 more elements

A method of generating an output clock signal having a frequency that is a predetermined multiple of the frequency of a periodic input clock signal, the method comprising:

generating a first clock signal by delaying an input clock signal by a first fixed delay time;
generating a second clock signal by delaying the input clock signal by the sum of the first fixed delay time and a second variable delay time;
generating a third clock signal by delaying the input clock signal by the sum of the first fixed delay time and a third variable delay time, the third variable delay time being a fixed multiple of the second variable delay time;
comparing the phase of the first clock signal with the phase of the third clock signal;
adjusting the variable delay times as a function of the phase comparison;
and
combining at least two of the first, second and third clock signals to generate the output clock signal.

4 more elements

Dependencies are inferred from the claim text.

Multi-phase clock signal generator and method having inherently unlimited frequency capability

Life of this patent

Multi-phase clock signal generator and method having inherently unlimited frequency capability

Life of this patent

Abstract

Claims52