US 2006/0140022 A1 · Data output circuit, data output method, and semiconductor memory device

Abstract

In a data output circuit, a data output method, and a semiconductor memory device, the data output circuit includes: an internal clock generation unit that delays an external clock signal by a first delay time to output an internal clock signal in response to the external clock signal and a replica data strobe signal; a data strobe signal output unit that outputs a data strobe signal in response to the internal clock signal; and a data strobe signal replication unit that delays the internal clock signal by a second delay time to output the replica data strobe signal and changing the second delay time in response to the data strobe signal and the replica data strobe signal. Accordingly, it is possible to save time and effort required for setting a delay time of a data strobe signal replication unit. In addition, it is possible to correct differences between packages of the delay time of the data strobe signal output unit.

Claims14

Dependent claims

A data output circuit comprising:

an internal clock generation unit that delays an external clock signal by a first delay time to output an internal clock signal in response to the external clock signal and a replica data strobe signal;
a data strobe signal output unit that outputs a data strobe signal in response to the internal clock signal;
and
a data strobe signal replication unit that delays the internal clock signal by a second delay time to output the replica data strobe signal and that changes the second delay time in response to the data strobe signal and the replica data strobe signal.

1 more element

A data output method of a data output circuit comprising an internal clock generation unit that delays an external clock signal by a first delay time to generate an internal clock signal, a data strobe signal output unit that outputs a data strobe signal by using the internal clock signal, and a data strobe signal replication unit that delays the internal clock signal by a second delay time to output a replica data strobe signal, the method comprising:

changing the second delay time in response to the data strobe signal and the replica data strobe signal;
and
changing the first delay time in response to the replica data strobe signal and the external clock signal.

A semiconductor memory device comprising:

an internal clock generation unit that delays an external clock signal by a first delay time to output an internal clock signal in response to the external clock signal and a replica data strobe signal;
a memory cell array having a plurality of memory cells to output data in response to an externally input read command;
a data output unit that inputs the data and that outputs output data, the data output unit outputting a data strobe signal in response to the internal clock signal;
and
a data strobe signal replication unit that delays the internal clock signal by a second delay time to output the replica data strobe signal and that changes the second delay time in response to the data strobe signal and the replica data strobe signal.

2 more elements

Dependencies are inferred from the claim text.

Data output circuit, data output method, and semiconductor memory device

Life of this patent

Data output circuit, data output method, and semiconductor memory device

Life of this patent

Abstract

Claims14