Circuit for generating data strobe signal of semiconductor memory device

Abstract

A circuit for generating a data strobe signal of a semiconductor memory device comprises a plurality of internal clock delay units, a selecting control unit and a pulse generating unit. The plurality of internal clock delay units delay an internal clock signal in response to a plurality of CAS latency signal. The selecting control unit logically combines a data latch control signal to latch input data with output signals from the plurality of internal clock delay units. The pulse generating unit generates the data strobe signal having a predetermined pulse in response to an output signal from the selecting control unit. In the circuit, a tDQSS margin is regulated depending on change of tCK of an operating frequency in response to a CAS latency signal.

Dependencies are inferred from the claim text.