Reduction of fusible links and associated circuitry on memory dies
AssigneeMicron Technology, Inc.
InventorsSujeet Ayyapureddi, Vasu Seeram
Life of this patent
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Abstract
The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among address banks that store memory addresses. Non-trial and error algorithms and techniques determine the number of addresses and the number of identical least significant bit (LSB) values that can share the same physical memory location. By sharing physical locations for identical LSB values, circuit hardware on a memory device (including fusible links and compare circuitry) is reduced. Thus, less die area is needed to provide the same degree of redundancy.
Claims4
A memory structure comprising a plurality of address banks, each said address bank operative to store a memory address, said structure comprising:
- a first subplurality of address banks that share physical memory locations for a first number of least significant bits;
- a second subplurality of address banks that share physical memory locations for a second number of least significant bits;
- and
- a third subplurality of address banks that share physical memory locations for a third number of least significant bits.
Dependencies are inferred from the claim text.