Static random access memory device having a memory cell with multiple bit elements

A static random access memory device comprising:

• a first bit-element;
• a second bit-element;
• first and second bit lines connected to the first and second bit-elements;
• a first set of access devices for respectively controlling communication between the first and second bit lines and the first bit-element;
• a second set of access devices for respectively controlling communication between the first and second bit lines and the second bit-element;
• and
• at least one word line for concurrently activating the first and second sets of access devices.

A random access memory array circuit comprising:

• a memory cell including a plurality of bit-elements, each bit-element including a bistable latch having a first inverter and a second inverter, wherein an input terminal of the first inverter is coupled to an output terminal of the second inverter at a true node, and wherein an input terminal of the second inverter is coupled to an output terminal of the first inverter at a complementary node;
• a plurality of first pass transistors, each coupled between a first bit line and the true node of a respective one of the plurality of bit-elements;
• a plurality of second pass transistors, each coupled between a second bit line and the complementary node of a respective one of the plurality of bit-elements;
• a word line connected to control terminals of each of the first and second pass transistors for simultaneously controlling communication between the plurality of bit-elements and the first and second bit lines;
• a plurality of third pass transistors, each coupled between a third bit line and the true node of a respective one of the plurality of bit-elements;
• a plurality of fourth pass transistors, each coupled between a fourth bit lien and the complementary node of a respective one of the plurality of bit-elements;
• and
• a second word line connected to control terminals of each of the third and fourth pass transistors for simultaneously controlling communication between the plurality of bit-elements and the third, and fourth bit lines.

A random access memory array circuit comprising:

• first and second communication lines;
• a first bit-element
• a second bit-element;
• a first set of access devices respectively coupled between the first bit-element and the first and second communication lines;
• a second set of access devices respectively coupled between the second bit-element and the first and second communication lines;
• an address line coupled to the first set of access devices for respectively controlling communication between the first bit-element and the first and second communication lines;
• and
• a selectable connection for coupling the address line to the second set of access devices for respectively controlling communication between the second bit-element and the first and second communication lines.

A static random access memory device comprising:

• a memory array having a plurality of memory cells arranged in a matrix of rows and columns;
• a plurality of word lines for activating respective rows of memory cells;
• an address decoder for receiving address data via a plurality of address data lines and activating word lines according to the received address data;
• and
• a selectable connection for coupling at least two of the address data lines.