Semiconductor memory device

A semiconductor memory device comprising a memory cell array with electrically rewritable and non-volatile memory cells arranged therein, and a bit line control circuit connected to a bit line of said memory cell array to control and detect the bit line voltage in accordance with operation modes, wherein

• said bit line control circuit comprises:
• a sense amplifier having a clamping transistor so disposed between a sense node and a bit line of said memory cell array as to serve for clamping and sensing the bit line voltage at a data read time;
• and
• a bit line select circuit having a bit line select transistor so disposed between the clamping transistor and a bit line as to select the bit line, the breakdown voltage of the bit line select transistor being higher than that of the clamping transistor, and wherein
• a connection node between the clamping transistor and the bit line select transistor is fixed in potential at a data erase time.

A semiconductor memory device comprising:

• a memory cell array with word lines and bit lines disposed as crossing each other and electrically rewritable and non-volatile memory cells disposed at the respective crossings of the word lines and bit lines;
• a sense amplifier disposed for a pair of bit lines of said memory cell array with a first kind of transistors;
• and
• a bit line select circuit disposed between said sense amplifier and the pair of bit lines with a second kind of transistors, breakdown voltage of which is higher than that of the first kind of transistors, wherein
• a clamping transistor serving for clamping and sensing the bit line voltage in said sense amplifier and a bit line select transistor in said bit line select circuit are connected in series between a sense node and a bit line, and connection node thereof is fixed in potential in a data erase mode.

A semiconductor memory device comprising:

• a memory cell array with a plurality of blocks, each block having electrically rewritable and non-volatile memory cells arranged therein;
• a sense amplifier configured to perform read data of said memory cell array, said sense amplifier having a first kind of transistors;
• and
• a bit line select circuit disposed between the bit lines of said memory cell array and said sense amplifier for selecting a bit line, said bit line select circuit having a second kind of transistors with a breakdown voltage higher than that of the first kind of transistors, wherein
• data erase is performed by a block of said memory cell array with applying an erase voltage to a well region, on which said memory cell array is formed, in such a state that the entire word lines in a selected block are applied with 0V;
• the entire bit lines are set in a floating state;
• and a connection node located between said sense amplifier and said bit line select circuit is fixed in potential.