Programming method for nanocrystal memory device
OwnerBohumil Lojekinventor
Life of this patent
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Abstract
A programming method for non-volatile electrically erasable and programmable CMOS memory transistor lowers programming power requirements. First, a nanocrystal floating gate is provided in electrical communication to source and drain electrodes of the transistor. Secondly, bipolar programming pulses are applied to the substrate, with a control gate held at a steady voltage. A first polarity partial cycle of the programming pulse creates space charge in the channel region between source and drain electrodes. A second polarity partial cycle drives at least a portion of the space charge onto the floating gate thereby establishing a charged state for the transistor corresponding to a binary digit. The non-charged state represents another binary digit.
Claims20
In a floating gate non-volatile transistor memory of the type having a p-well substrate spaced apart from n-plus source and drain electrodes in the substrate, the programming method comprising:
- providing a floating gate in proximity to the substrate wherein electrically conductive nanocrystals are embedded in dielectric material, the nanocrystals being in electric field communication with at least one of the source and drain electrodes, and a conductive control gate is disposed over the dielectric material, and
- applying a bipolar voltage pulse to the substrate while the control gate is held at a positive voltage, the bipolar pulses have a positive value in the range of 0.5 to 1.5 volts and a negative value in the range of −3.5 volts to −4.5 volts.
A programming method for a nanocrystal memory CMOS transistor device of the type having source, drain and a channel therebetween, with a nanocrystal floating gate and a control gate, the method comprising:
- establishing a space charge region in the channel region of the device on a first partial cycle of a bipolar programming pulse involving positive and negative voltage polarities on sequential partial cycles applied at locations on opposite sides of the channel, and
- accelerating charge from the space charge region to the nanocrystal floating gate on a second partial cycle of the bipolar programming pulse applied at the same locations.
A programming method for a nanocrystal memory CMOS transistor device of the type having source, drain and a channel therebetween, with a nanocrystal floating gate and a control gate, the method comprising:
- providing an auxiliary electrode near source and drain electrodes to at least partially create a space charge region in the channel region of the device on a first partial cycle of a bipolar programming pulse involving positive and negative voltage polarities on sequential partial cycles applied at locations on opposite sides of the channel, and
- accelerating charge from the space charge region to the nanocrystal floating gate on a second partial cycle of the bipolar programming pulse applied at the same locations.
Dependencies are inferred from the claim text.