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AssigneeMacronix International Co., Ltd.
InventorsYi Liao, Chih Yeh, Wen Tsai
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A method of reducing gate disturb in a charge-trapping layer memory cell by applying different Vpass voltages to different sides of a selected wordline. A higher Vpass voltage is used to pass higher source/drain voltage and a lower Vpass voltage is used to pass a lower source/drain voltage. By controlling the Vpass voltages on different sides of a selected wordline, it is possible to reduce a vertical field that is established in a gate region when the Vpass voltages are applied. A reduced vertical field results in suppressed gate disturb. The method also includes a novel bit-line biasing scheme that may further reduce the vertical field and thereby may further suppress gate disturb, particularly in an array of memory cells.
A method of operating a plurality of memory cells each comprising a charge trapping layer, the memory cells being selectable via bit-lines and wordlines, the method comprising:
A method of reducing gate disturb in a memory cell, the method comprising:
A method of operating an array of charge trapping layer memory cells, the method comprising:
Dependencies are inferred from the claim text.