Flash memory device
AssigneeHynix Semiconductor Inc.
InventorsHee Park, Kyeong Lee, Byung Park
Life of this patent
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Abstract
A flash memory device comprises a first group of dummy memory cells disposed between source selection transistors, which are coupled to a source selection line, and memory cells coupled to a first wordline. The flash memory device further comprises a second group of dummy memory cells disposed between drain selection transistors, which are coupled to a drain selection line, and memory cells coupled to the last wordline. The flash memory device is configured to prevent program disturbance in deselected cell strings and degradation of programming/erasing speeds in a selected cell string.
Claims26
A flash memory device comprising:
- a first selection transistor coupled to a bitline;
- a second selection transistor coupled to a common source line;
- a plurality of memory cells coupled between the first and second selection transistors, each memory cell being coupled to a wordline, and
- a dummy memory cell provided between one of the memory cells and the second selection transistor.
A flash memory device comprising:
- first selection transistors each coupled to a plurality of bitlines;
- second selection transistors coupled to a common source line;
- and
- a plurality of memory cell arrays provided between the first and second selection transistors, each memory cell array provided between each first selection transistor and each second selection transistor;
- and
- a plurality of wordlines, each wordline being coupled to a plurality of memory cells in different memory cell arrays,
- wherein each memory cell array includes at least one dummy memory cell.
A flash memory device comprising:
- first selection transistors each coupled to a plurality of bitlines;
- second selection transistors coupled to a common source line;
- and
- a plurality of memory cells coupled between the first and second selection transistors and coupled to a plurality of wordlines,
- wherein the plurality of memory cells include a first group of dummy memory cells coupled between memory cells coupled to a first wordline and the second selection transistors, and the plurality of memory cells further include a second group of dummy memory cells coupled between memory cells coupled to a last wordline and the first selection transistors.
Dependencies are inferred from the claim text.